198568f0fSGraeme Russ /* 298568f0fSGraeme Russ * Taken from the linux kernel file of the same name 398568f0fSGraeme Russ * 498568f0fSGraeme Russ * (C) Copyright 2012 598568f0fSGraeme Russ * Graeme Russ, <graeme.russ@gmail.com> 698568f0fSGraeme Russ * 7*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 898568f0fSGraeme Russ */ 998568f0fSGraeme Russ 1098568f0fSGraeme Russ #ifndef _ASM_X86_MSR_INDEX_H 1198568f0fSGraeme Russ #define _ASM_X86_MSR_INDEX_H 1298568f0fSGraeme Russ 1398568f0fSGraeme Russ /* CPU model specific register (MSR) numbers */ 1498568f0fSGraeme Russ 1598568f0fSGraeme Russ /* x86-64 specific MSRs */ 1698568f0fSGraeme Russ #define MSR_EFER 0xc0000080 /* extended feature register */ 1798568f0fSGraeme Russ #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 1898568f0fSGraeme Russ #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 1998568f0fSGraeme Russ #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 2098568f0fSGraeme Russ #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 2198568f0fSGraeme Russ #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 2298568f0fSGraeme Russ #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 2398568f0fSGraeme Russ #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 2498568f0fSGraeme Russ #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 2598568f0fSGraeme Russ 2698568f0fSGraeme Russ /* EFER bits: */ 2798568f0fSGraeme Russ #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 2898568f0fSGraeme Russ #define _EFER_LME 8 /* Long mode enable */ 2998568f0fSGraeme Russ #define _EFER_LMA 10 /* Long mode active (read-only) */ 3098568f0fSGraeme Russ #define _EFER_NX 11 /* No execute enable */ 3198568f0fSGraeme Russ #define _EFER_SVME 12 /* Enable virtualization */ 3298568f0fSGraeme Russ #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 3398568f0fSGraeme Russ #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 3498568f0fSGraeme Russ 3598568f0fSGraeme Russ #define EFER_SCE (1<<_EFER_SCE) 3698568f0fSGraeme Russ #define EFER_LME (1<<_EFER_LME) 3798568f0fSGraeme Russ #define EFER_LMA (1<<_EFER_LMA) 3898568f0fSGraeme Russ #define EFER_NX (1<<_EFER_NX) 3998568f0fSGraeme Russ #define EFER_SVME (1<<_EFER_SVME) 4098568f0fSGraeme Russ #define EFER_LMSLE (1<<_EFER_LMSLE) 4198568f0fSGraeme Russ #define EFER_FFXSR (1<<_EFER_FFXSR) 4298568f0fSGraeme Russ 4398568f0fSGraeme Russ /* Intel MSRs. Some also available on other CPUs */ 4498568f0fSGraeme Russ #define MSR_IA32_PERFCTR0 0x000000c1 4598568f0fSGraeme Russ #define MSR_IA32_PERFCTR1 0x000000c2 4698568f0fSGraeme Russ #define MSR_FSB_FREQ 0x000000cd 4798568f0fSGraeme Russ 4898568f0fSGraeme Russ #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 4998568f0fSGraeme Russ #define NHM_C3_AUTO_DEMOTE (1UL << 25) 5098568f0fSGraeme Russ #define NHM_C1_AUTO_DEMOTE (1UL << 26) 5198568f0fSGraeme Russ #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 5298568f0fSGraeme Russ 5398568f0fSGraeme Russ #define MSR_MTRRcap 0x000000fe 5498568f0fSGraeme Russ #define MSR_IA32_BBL_CR_CTL 0x00000119 5598568f0fSGraeme Russ #define MSR_IA32_BBL_CR_CTL3 0x0000011e 5698568f0fSGraeme Russ 5798568f0fSGraeme Russ #define MSR_IA32_SYSENTER_CS 0x00000174 5898568f0fSGraeme Russ #define MSR_IA32_SYSENTER_ESP 0x00000175 5998568f0fSGraeme Russ #define MSR_IA32_SYSENTER_EIP 0x00000176 6098568f0fSGraeme Russ 6198568f0fSGraeme Russ #define MSR_IA32_MCG_CAP 0x00000179 6298568f0fSGraeme Russ #define MSR_IA32_MCG_STATUS 0x0000017a 6398568f0fSGraeme Russ #define MSR_IA32_MCG_CTL 0x0000017b 6498568f0fSGraeme Russ 6598568f0fSGraeme Russ #define MSR_OFFCORE_RSP_0 0x000001a6 6698568f0fSGraeme Russ #define MSR_OFFCORE_RSP_1 0x000001a7 6798568f0fSGraeme Russ 6898568f0fSGraeme Russ #define MSR_IA32_PEBS_ENABLE 0x000003f1 6998568f0fSGraeme Russ #define MSR_IA32_DS_AREA 0x00000600 7098568f0fSGraeme Russ #define MSR_IA32_PERF_CAPABILITIES 0x00000345 7198568f0fSGraeme Russ 7298568f0fSGraeme Russ #define MSR_MTRRfix64K_00000 0x00000250 7398568f0fSGraeme Russ #define MSR_MTRRfix16K_80000 0x00000258 7498568f0fSGraeme Russ #define MSR_MTRRfix16K_A0000 0x00000259 7598568f0fSGraeme Russ #define MSR_MTRRfix4K_C0000 0x00000268 7698568f0fSGraeme Russ #define MSR_MTRRfix4K_C8000 0x00000269 7798568f0fSGraeme Russ #define MSR_MTRRfix4K_D0000 0x0000026a 7898568f0fSGraeme Russ #define MSR_MTRRfix4K_D8000 0x0000026b 7998568f0fSGraeme Russ #define MSR_MTRRfix4K_E0000 0x0000026c 8098568f0fSGraeme Russ #define MSR_MTRRfix4K_E8000 0x0000026d 8198568f0fSGraeme Russ #define MSR_MTRRfix4K_F0000 0x0000026e 8298568f0fSGraeme Russ #define MSR_MTRRfix4K_F8000 0x0000026f 8398568f0fSGraeme Russ #define MSR_MTRRdefType 0x000002ff 8498568f0fSGraeme Russ 8598568f0fSGraeme Russ #define MSR_IA32_CR_PAT 0x00000277 8698568f0fSGraeme Russ 8798568f0fSGraeme Russ #define MSR_IA32_DEBUGCTLMSR 0x000001d9 8898568f0fSGraeme Russ #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 8998568f0fSGraeme Russ #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 9098568f0fSGraeme Russ #define MSR_IA32_LASTINTFROMIP 0x000001dd 9198568f0fSGraeme Russ #define MSR_IA32_LASTINTTOIP 0x000001de 9298568f0fSGraeme Russ 9398568f0fSGraeme Russ /* DEBUGCTLMSR bits (others vary by model): */ 9498568f0fSGraeme Russ #define DEBUGCTLMSR_LBR (1UL << 0) 9598568f0fSGraeme Russ #define DEBUGCTLMSR_BTF (1UL << 1) 9698568f0fSGraeme Russ #define DEBUGCTLMSR_TR (1UL << 6) 9798568f0fSGraeme Russ #define DEBUGCTLMSR_BTS (1UL << 7) 9898568f0fSGraeme Russ #define DEBUGCTLMSR_BTINT (1UL << 8) 9998568f0fSGraeme Russ #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 10098568f0fSGraeme Russ #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 10198568f0fSGraeme Russ #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 10298568f0fSGraeme Russ 10398568f0fSGraeme Russ #define MSR_IA32_MC0_CTL 0x00000400 10498568f0fSGraeme Russ #define MSR_IA32_MC0_STATUS 0x00000401 10598568f0fSGraeme Russ #define MSR_IA32_MC0_ADDR 0x00000402 10698568f0fSGraeme Russ #define MSR_IA32_MC0_MISC 0x00000403 10798568f0fSGraeme Russ 10898568f0fSGraeme Russ #define MSR_AMD64_MC0_MASK 0xc0010044 10998568f0fSGraeme Russ 11098568f0fSGraeme Russ #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 11198568f0fSGraeme Russ #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 11298568f0fSGraeme Russ #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 11398568f0fSGraeme Russ #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 11498568f0fSGraeme Russ 11598568f0fSGraeme Russ #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 11698568f0fSGraeme Russ 11798568f0fSGraeme Russ /* These are consecutive and not in the normal 4er MCE bank block */ 11898568f0fSGraeme Russ #define MSR_IA32_MC0_CTL2 0x00000280 11998568f0fSGraeme Russ #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 12098568f0fSGraeme Russ 12198568f0fSGraeme Russ #define MSR_P6_PERFCTR0 0x000000c1 12298568f0fSGraeme Russ #define MSR_P6_PERFCTR1 0x000000c2 12398568f0fSGraeme Russ #define MSR_P6_EVNTSEL0 0x00000186 12498568f0fSGraeme Russ #define MSR_P6_EVNTSEL1 0x00000187 12598568f0fSGraeme Russ 12698568f0fSGraeme Russ /* AMD64 MSRs. Not complete. See the architecture manual for a more 12798568f0fSGraeme Russ complete list. */ 12898568f0fSGraeme Russ 12998568f0fSGraeme Russ #define MSR_AMD64_PATCH_LEVEL 0x0000008b 13098568f0fSGraeme Russ #define MSR_AMD64_NB_CFG 0xc001001f 13198568f0fSGraeme Russ #define MSR_AMD64_PATCH_LOADER 0xc0010020 13298568f0fSGraeme Russ #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 13398568f0fSGraeme Russ #define MSR_AMD64_OSVW_STATUS 0xc0010141 13498568f0fSGraeme Russ #define MSR_AMD64_DC_CFG 0xc0011022 13598568f0fSGraeme Russ #define MSR_AMD64_IBSFETCHCTL 0xc0011030 13698568f0fSGraeme Russ #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 13798568f0fSGraeme Russ #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 13898568f0fSGraeme Russ #define MSR_AMD64_IBSOPCTL 0xc0011033 13998568f0fSGraeme Russ #define MSR_AMD64_IBSOPRIP 0xc0011034 14098568f0fSGraeme Russ #define MSR_AMD64_IBSOPDATA 0xc0011035 14198568f0fSGraeme Russ #define MSR_AMD64_IBSOPDATA2 0xc0011036 14298568f0fSGraeme Russ #define MSR_AMD64_IBSOPDATA3 0xc0011037 14398568f0fSGraeme Russ #define MSR_AMD64_IBSDCLINAD 0xc0011038 14498568f0fSGraeme Russ #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 14598568f0fSGraeme Russ #define MSR_AMD64_IBSCTL 0xc001103a 14698568f0fSGraeme Russ #define MSR_AMD64_IBSBRTARGET 0xc001103b 14798568f0fSGraeme Russ 14898568f0fSGraeme Russ /* Fam 15h MSRs */ 14998568f0fSGraeme Russ #define MSR_F15H_PERF_CTL 0xc0010200 15098568f0fSGraeme Russ #define MSR_F15H_PERF_CTR 0xc0010201 15198568f0fSGraeme Russ 15298568f0fSGraeme Russ /* Fam 10h MSRs */ 15398568f0fSGraeme Russ #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 15498568f0fSGraeme Russ #define FAM10H_MMIO_CONF_ENABLE (1<<0) 15598568f0fSGraeme Russ #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 15698568f0fSGraeme Russ #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 15798568f0fSGraeme Russ #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 15898568f0fSGraeme Russ #define FAM10H_MMIO_CONF_BASE_SHIFT 20 15998568f0fSGraeme Russ #define MSR_FAM10H_NODE_ID 0xc001100c 16098568f0fSGraeme Russ 16198568f0fSGraeme Russ /* K8 MSRs */ 16298568f0fSGraeme Russ #define MSR_K8_TOP_MEM1 0xc001001a 16398568f0fSGraeme Russ #define MSR_K8_TOP_MEM2 0xc001001d 16498568f0fSGraeme Russ #define MSR_K8_SYSCFG 0xc0010010 16598568f0fSGraeme Russ #define MSR_K8_INT_PENDING_MSG 0xc0010055 16698568f0fSGraeme Russ /* C1E active bits in int pending message */ 16798568f0fSGraeme Russ #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 16898568f0fSGraeme Russ #define MSR_K8_TSEG_ADDR 0xc0010112 16998568f0fSGraeme Russ #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 17098568f0fSGraeme Russ #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 17198568f0fSGraeme Russ #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 17298568f0fSGraeme Russ 17398568f0fSGraeme Russ /* K7 MSRs */ 17498568f0fSGraeme Russ #define MSR_K7_EVNTSEL0 0xc0010000 17598568f0fSGraeme Russ #define MSR_K7_PERFCTR0 0xc0010004 17698568f0fSGraeme Russ #define MSR_K7_EVNTSEL1 0xc0010001 17798568f0fSGraeme Russ #define MSR_K7_PERFCTR1 0xc0010005 17898568f0fSGraeme Russ #define MSR_K7_EVNTSEL2 0xc0010002 17998568f0fSGraeme Russ #define MSR_K7_PERFCTR2 0xc0010006 18098568f0fSGraeme Russ #define MSR_K7_EVNTSEL3 0xc0010003 18198568f0fSGraeme Russ #define MSR_K7_PERFCTR3 0xc0010007 18298568f0fSGraeme Russ #define MSR_K7_CLK_CTL 0xc001001b 18398568f0fSGraeme Russ #define MSR_K7_HWCR 0xc0010015 18498568f0fSGraeme Russ #define MSR_K7_FID_VID_CTL 0xc0010041 18598568f0fSGraeme Russ #define MSR_K7_FID_VID_STATUS 0xc0010042 18698568f0fSGraeme Russ 18798568f0fSGraeme Russ /* K6 MSRs */ 18898568f0fSGraeme Russ #define MSR_K6_WHCR 0xc0000082 18998568f0fSGraeme Russ #define MSR_K6_UWCCR 0xc0000085 19098568f0fSGraeme Russ #define MSR_K6_EPMR 0xc0000086 19198568f0fSGraeme Russ #define MSR_K6_PSOR 0xc0000087 19298568f0fSGraeme Russ #define MSR_K6_PFIR 0xc0000088 19398568f0fSGraeme Russ 19498568f0fSGraeme Russ /* Centaur-Hauls/IDT defined MSRs. */ 19598568f0fSGraeme Russ #define MSR_IDT_FCR1 0x00000107 19698568f0fSGraeme Russ #define MSR_IDT_FCR2 0x00000108 19798568f0fSGraeme Russ #define MSR_IDT_FCR3 0x00000109 19898568f0fSGraeme Russ #define MSR_IDT_FCR4 0x0000010a 19998568f0fSGraeme Russ 20098568f0fSGraeme Russ #define MSR_IDT_MCR0 0x00000110 20198568f0fSGraeme Russ #define MSR_IDT_MCR1 0x00000111 20298568f0fSGraeme Russ #define MSR_IDT_MCR2 0x00000112 20398568f0fSGraeme Russ #define MSR_IDT_MCR3 0x00000113 20498568f0fSGraeme Russ #define MSR_IDT_MCR4 0x00000114 20598568f0fSGraeme Russ #define MSR_IDT_MCR5 0x00000115 20698568f0fSGraeme Russ #define MSR_IDT_MCR6 0x00000116 20798568f0fSGraeme Russ #define MSR_IDT_MCR7 0x00000117 20898568f0fSGraeme Russ #define MSR_IDT_MCR_CTRL 0x00000120 20998568f0fSGraeme Russ 21098568f0fSGraeme Russ /* VIA Cyrix defined MSRs*/ 21198568f0fSGraeme Russ #define MSR_VIA_FCR 0x00001107 21298568f0fSGraeme Russ #define MSR_VIA_LONGHAUL 0x0000110a 21398568f0fSGraeme Russ #define MSR_VIA_RNG 0x0000110b 21498568f0fSGraeme Russ #define MSR_VIA_BCR2 0x00001147 21598568f0fSGraeme Russ 21698568f0fSGraeme Russ /* Transmeta defined MSRs */ 21798568f0fSGraeme Russ #define MSR_TMTA_LONGRUN_CTRL 0x80868010 21898568f0fSGraeme Russ #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 21998568f0fSGraeme Russ #define MSR_TMTA_LRTI_READOUT 0x80868018 22098568f0fSGraeme Russ #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 22198568f0fSGraeme Russ 22298568f0fSGraeme Russ /* Intel defined MSRs. */ 22398568f0fSGraeme Russ #define MSR_IA32_P5_MC_ADDR 0x00000000 22498568f0fSGraeme Russ #define MSR_IA32_P5_MC_TYPE 0x00000001 22598568f0fSGraeme Russ #define MSR_IA32_TSC 0x00000010 22698568f0fSGraeme Russ #define MSR_IA32_PLATFORM_ID 0x00000017 22798568f0fSGraeme Russ #define MSR_IA32_EBL_CR_POWERON 0x0000002a 22898568f0fSGraeme Russ #define MSR_EBC_FREQUENCY_ID 0x0000002c 22998568f0fSGraeme Russ #define MSR_IA32_FEATURE_CONTROL 0x0000003a 23098568f0fSGraeme Russ 23198568f0fSGraeme Russ #define FEATURE_CONTROL_LOCKED (1<<0) 23298568f0fSGraeme Russ #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 23398568f0fSGraeme Russ #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 23498568f0fSGraeme Russ 23598568f0fSGraeme Russ #define MSR_IA32_APICBASE 0x0000001b 23698568f0fSGraeme Russ #define MSR_IA32_APICBASE_BSP (1<<8) 23798568f0fSGraeme Russ #define MSR_IA32_APICBASE_ENABLE (1<<11) 23898568f0fSGraeme Russ #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 23998568f0fSGraeme Russ 24098568f0fSGraeme Russ #define MSR_IA32_UCODE_WRITE 0x00000079 24198568f0fSGraeme Russ #define MSR_IA32_UCODE_REV 0x0000008b 24298568f0fSGraeme Russ 24398568f0fSGraeme Russ #define MSR_IA32_PERF_STATUS 0x00000198 24498568f0fSGraeme Russ #define MSR_IA32_PERF_CTL 0x00000199 24598568f0fSGraeme Russ 24698568f0fSGraeme Russ #define MSR_IA32_MPERF 0x000000e7 24798568f0fSGraeme Russ #define MSR_IA32_APERF 0x000000e8 24898568f0fSGraeme Russ 24998568f0fSGraeme Russ #define MSR_IA32_THERM_CONTROL 0x0000019a 25098568f0fSGraeme Russ #define MSR_IA32_THERM_INTERRUPT 0x0000019b 25198568f0fSGraeme Russ 25298568f0fSGraeme Russ #define THERM_INT_HIGH_ENABLE (1 << 0) 25398568f0fSGraeme Russ #define THERM_INT_LOW_ENABLE (1 << 1) 25498568f0fSGraeme Russ #define THERM_INT_PLN_ENABLE (1 << 24) 25598568f0fSGraeme Russ 25698568f0fSGraeme Russ #define MSR_IA32_THERM_STATUS 0x0000019c 25798568f0fSGraeme Russ 25898568f0fSGraeme Russ #define THERM_STATUS_PROCHOT (1 << 0) 25998568f0fSGraeme Russ #define THERM_STATUS_POWER_LIMIT (1 << 10) 26098568f0fSGraeme Russ 26198568f0fSGraeme Russ #define MSR_THERM2_CTL 0x0000019d 26298568f0fSGraeme Russ 26398568f0fSGraeme Russ #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 26498568f0fSGraeme Russ 26598568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE 0x000001a0 26698568f0fSGraeme Russ 26798568f0fSGraeme Russ #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 26898568f0fSGraeme Russ 26998568f0fSGraeme Russ #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 27098568f0fSGraeme Russ 27198568f0fSGraeme Russ #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 27298568f0fSGraeme Russ 27398568f0fSGraeme Russ #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 27498568f0fSGraeme Russ #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 27598568f0fSGraeme Russ 27698568f0fSGraeme Russ #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 27798568f0fSGraeme Russ 27898568f0fSGraeme Russ #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 27998568f0fSGraeme Russ #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 28098568f0fSGraeme Russ #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 28198568f0fSGraeme Russ 28298568f0fSGraeme Russ /* Thermal Thresholds Support */ 28398568f0fSGraeme Russ #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 28498568f0fSGraeme Russ #define THERM_SHIFT_THRESHOLD0 8 28598568f0fSGraeme Russ #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 28698568f0fSGraeme Russ #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 28798568f0fSGraeme Russ #define THERM_SHIFT_THRESHOLD1 16 28898568f0fSGraeme Russ #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 28998568f0fSGraeme Russ #define THERM_STATUS_THRESHOLD0 (1 << 6) 29098568f0fSGraeme Russ #define THERM_LOG_THRESHOLD0 (1 << 7) 29198568f0fSGraeme Russ #define THERM_STATUS_THRESHOLD1 (1 << 8) 29298568f0fSGraeme Russ #define THERM_LOG_THRESHOLD1 (1 << 9) 29398568f0fSGraeme Russ 29498568f0fSGraeme Russ /* MISC_ENABLE bits: architectural */ 29598568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) 29698568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) 29798568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) 29898568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) 29998568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) 30098568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) 30198568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 30298568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) 30398568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) 30498568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) 30598568f0fSGraeme Russ 30698568f0fSGraeme Russ /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 30798568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) 30898568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) 30998568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) 31098568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) 31198568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) 31298568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) 31398568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) 31498568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) 31598568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) 31698568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) 31798568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) 31898568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) 31998568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) 32098568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) 32198568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) 32298568f0fSGraeme Russ 32398568f0fSGraeme Russ /* P4/Xeon+ specific */ 32498568f0fSGraeme Russ #define MSR_IA32_MCG_EAX 0x00000180 32598568f0fSGraeme Russ #define MSR_IA32_MCG_EBX 0x00000181 32698568f0fSGraeme Russ #define MSR_IA32_MCG_ECX 0x00000182 32798568f0fSGraeme Russ #define MSR_IA32_MCG_EDX 0x00000183 32898568f0fSGraeme Russ #define MSR_IA32_MCG_ESI 0x00000184 32998568f0fSGraeme Russ #define MSR_IA32_MCG_EDI 0x00000185 33098568f0fSGraeme Russ #define MSR_IA32_MCG_EBP 0x00000186 33198568f0fSGraeme Russ #define MSR_IA32_MCG_ESP 0x00000187 33298568f0fSGraeme Russ #define MSR_IA32_MCG_EFLAGS 0x00000188 33398568f0fSGraeme Russ #define MSR_IA32_MCG_EIP 0x00000189 33498568f0fSGraeme Russ #define MSR_IA32_MCG_RESERVED 0x0000018a 33598568f0fSGraeme Russ 33698568f0fSGraeme Russ /* Pentium IV performance counter MSRs */ 33798568f0fSGraeme Russ #define MSR_P4_BPU_PERFCTR0 0x00000300 33898568f0fSGraeme Russ #define MSR_P4_BPU_PERFCTR1 0x00000301 33998568f0fSGraeme Russ #define MSR_P4_BPU_PERFCTR2 0x00000302 34098568f0fSGraeme Russ #define MSR_P4_BPU_PERFCTR3 0x00000303 34198568f0fSGraeme Russ #define MSR_P4_MS_PERFCTR0 0x00000304 34298568f0fSGraeme Russ #define MSR_P4_MS_PERFCTR1 0x00000305 34398568f0fSGraeme Russ #define MSR_P4_MS_PERFCTR2 0x00000306 34498568f0fSGraeme Russ #define MSR_P4_MS_PERFCTR3 0x00000307 34598568f0fSGraeme Russ #define MSR_P4_FLAME_PERFCTR0 0x00000308 34698568f0fSGraeme Russ #define MSR_P4_FLAME_PERFCTR1 0x00000309 34798568f0fSGraeme Russ #define MSR_P4_FLAME_PERFCTR2 0x0000030a 34898568f0fSGraeme Russ #define MSR_P4_FLAME_PERFCTR3 0x0000030b 34998568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR0 0x0000030c 35098568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR1 0x0000030d 35198568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR2 0x0000030e 35298568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR3 0x0000030f 35398568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR4 0x00000310 35498568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR5 0x00000311 35598568f0fSGraeme Russ #define MSR_P4_BPU_CCCR0 0x00000360 35698568f0fSGraeme Russ #define MSR_P4_BPU_CCCR1 0x00000361 35798568f0fSGraeme Russ #define MSR_P4_BPU_CCCR2 0x00000362 35898568f0fSGraeme Russ #define MSR_P4_BPU_CCCR3 0x00000363 35998568f0fSGraeme Russ #define MSR_P4_MS_CCCR0 0x00000364 36098568f0fSGraeme Russ #define MSR_P4_MS_CCCR1 0x00000365 36198568f0fSGraeme Russ #define MSR_P4_MS_CCCR2 0x00000366 36298568f0fSGraeme Russ #define MSR_P4_MS_CCCR3 0x00000367 36398568f0fSGraeme Russ #define MSR_P4_FLAME_CCCR0 0x00000368 36498568f0fSGraeme Russ #define MSR_P4_FLAME_CCCR1 0x00000369 36598568f0fSGraeme Russ #define MSR_P4_FLAME_CCCR2 0x0000036a 36698568f0fSGraeme Russ #define MSR_P4_FLAME_CCCR3 0x0000036b 36798568f0fSGraeme Russ #define MSR_P4_IQ_CCCR0 0x0000036c 36898568f0fSGraeme Russ #define MSR_P4_IQ_CCCR1 0x0000036d 36998568f0fSGraeme Russ #define MSR_P4_IQ_CCCR2 0x0000036e 37098568f0fSGraeme Russ #define MSR_P4_IQ_CCCR3 0x0000036f 37198568f0fSGraeme Russ #define MSR_P4_IQ_CCCR4 0x00000370 37298568f0fSGraeme Russ #define MSR_P4_IQ_CCCR5 0x00000371 37398568f0fSGraeme Russ #define MSR_P4_ALF_ESCR0 0x000003ca 37498568f0fSGraeme Russ #define MSR_P4_ALF_ESCR1 0x000003cb 37598568f0fSGraeme Russ #define MSR_P4_BPU_ESCR0 0x000003b2 37698568f0fSGraeme Russ #define MSR_P4_BPU_ESCR1 0x000003b3 37798568f0fSGraeme Russ #define MSR_P4_BSU_ESCR0 0x000003a0 37898568f0fSGraeme Russ #define MSR_P4_BSU_ESCR1 0x000003a1 37998568f0fSGraeme Russ #define MSR_P4_CRU_ESCR0 0x000003b8 38098568f0fSGraeme Russ #define MSR_P4_CRU_ESCR1 0x000003b9 38198568f0fSGraeme Russ #define MSR_P4_CRU_ESCR2 0x000003cc 38298568f0fSGraeme Russ #define MSR_P4_CRU_ESCR3 0x000003cd 38398568f0fSGraeme Russ #define MSR_P4_CRU_ESCR4 0x000003e0 38498568f0fSGraeme Russ #define MSR_P4_CRU_ESCR5 0x000003e1 38598568f0fSGraeme Russ #define MSR_P4_DAC_ESCR0 0x000003a8 38698568f0fSGraeme Russ #define MSR_P4_DAC_ESCR1 0x000003a9 38798568f0fSGraeme Russ #define MSR_P4_FIRM_ESCR0 0x000003a4 38898568f0fSGraeme Russ #define MSR_P4_FIRM_ESCR1 0x000003a5 38998568f0fSGraeme Russ #define MSR_P4_FLAME_ESCR0 0x000003a6 39098568f0fSGraeme Russ #define MSR_P4_FLAME_ESCR1 0x000003a7 39198568f0fSGraeme Russ #define MSR_P4_FSB_ESCR0 0x000003a2 39298568f0fSGraeme Russ #define MSR_P4_FSB_ESCR1 0x000003a3 39398568f0fSGraeme Russ #define MSR_P4_IQ_ESCR0 0x000003ba 39498568f0fSGraeme Russ #define MSR_P4_IQ_ESCR1 0x000003bb 39598568f0fSGraeme Russ #define MSR_P4_IS_ESCR0 0x000003b4 39698568f0fSGraeme Russ #define MSR_P4_IS_ESCR1 0x000003b5 39798568f0fSGraeme Russ #define MSR_P4_ITLB_ESCR0 0x000003b6 39898568f0fSGraeme Russ #define MSR_P4_ITLB_ESCR1 0x000003b7 39998568f0fSGraeme Russ #define MSR_P4_IX_ESCR0 0x000003c8 40098568f0fSGraeme Russ #define MSR_P4_IX_ESCR1 0x000003c9 40198568f0fSGraeme Russ #define MSR_P4_MOB_ESCR0 0x000003aa 40298568f0fSGraeme Russ #define MSR_P4_MOB_ESCR1 0x000003ab 40398568f0fSGraeme Russ #define MSR_P4_MS_ESCR0 0x000003c0 40498568f0fSGraeme Russ #define MSR_P4_MS_ESCR1 0x000003c1 40598568f0fSGraeme Russ #define MSR_P4_PMH_ESCR0 0x000003ac 40698568f0fSGraeme Russ #define MSR_P4_PMH_ESCR1 0x000003ad 40798568f0fSGraeme Russ #define MSR_P4_RAT_ESCR0 0x000003bc 40898568f0fSGraeme Russ #define MSR_P4_RAT_ESCR1 0x000003bd 40998568f0fSGraeme Russ #define MSR_P4_SAAT_ESCR0 0x000003ae 41098568f0fSGraeme Russ #define MSR_P4_SAAT_ESCR1 0x000003af 41198568f0fSGraeme Russ #define MSR_P4_SSU_ESCR0 0x000003be 41298568f0fSGraeme Russ #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 41398568f0fSGraeme Russ 41498568f0fSGraeme Russ #define MSR_P4_TBPU_ESCR0 0x000003c2 41598568f0fSGraeme Russ #define MSR_P4_TBPU_ESCR1 0x000003c3 41698568f0fSGraeme Russ #define MSR_P4_TC_ESCR0 0x000003c4 41798568f0fSGraeme Russ #define MSR_P4_TC_ESCR1 0x000003c5 41898568f0fSGraeme Russ #define MSR_P4_U2L_ESCR0 0x000003b0 41998568f0fSGraeme Russ #define MSR_P4_U2L_ESCR1 0x000003b1 42098568f0fSGraeme Russ 42198568f0fSGraeme Russ #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 42298568f0fSGraeme Russ 42398568f0fSGraeme Russ /* Intel Core-based CPU performance counters */ 42498568f0fSGraeme Russ #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 42598568f0fSGraeme Russ #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 42698568f0fSGraeme Russ #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 42798568f0fSGraeme Russ #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 42898568f0fSGraeme Russ #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 42998568f0fSGraeme Russ #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 43098568f0fSGraeme Russ #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 43198568f0fSGraeme Russ 43298568f0fSGraeme Russ /* Geode defined MSRs */ 43398568f0fSGraeme Russ #define MSR_GEODE_BUSCONT_CONF0 0x00001900 43498568f0fSGraeme Russ 43598568f0fSGraeme Russ /* Intel VT MSRs */ 43698568f0fSGraeme Russ #define MSR_IA32_VMX_BASIC 0x00000480 43798568f0fSGraeme Russ #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 43898568f0fSGraeme Russ #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 43998568f0fSGraeme Russ #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 44098568f0fSGraeme Russ #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 44198568f0fSGraeme Russ #define MSR_IA32_VMX_MISC 0x00000485 44298568f0fSGraeme Russ #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 44398568f0fSGraeme Russ #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 44498568f0fSGraeme Russ #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 44598568f0fSGraeme Russ #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 44698568f0fSGraeme Russ #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 44798568f0fSGraeme Russ #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 44898568f0fSGraeme Russ #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 44998568f0fSGraeme Russ 45098568f0fSGraeme Russ /* AMD-V MSRs */ 45198568f0fSGraeme Russ 45298568f0fSGraeme Russ #define MSR_VM_CR 0xc0010114 45398568f0fSGraeme Russ #define MSR_VM_IGNNE 0xc0010115 45498568f0fSGraeme Russ #define MSR_VM_HSAVE_PA 0xc0010117 45598568f0fSGraeme Russ 45698568f0fSGraeme Russ #endif /* _ASM_X86_MSR_INDEX_H */ 457