1*f6220f1aSBin Meng /* 2*f6220f1aSBin Meng * Copyright (c) 2014 Google, Inc 3*f6220f1aSBin Meng * 4*f6220f1aSBin Meng * SPDX-License-Identifier: GPL-2.0+ 5*f6220f1aSBin Meng */ 6*f6220f1aSBin Meng 7*f6220f1aSBin Meng #ifndef _ASM_ARCH_MRCCACHE_H 8*f6220f1aSBin Meng #define _ASM_ARCH_MRCCACHE_H 9*f6220f1aSBin Meng 10*f6220f1aSBin Meng #define MRC_DATA_ALIGN 0x1000 11*f6220f1aSBin Meng #define MRC_DATA_SIGNATURE (('M' << 0) | ('R' << 8) | ('C' << 16) | \ 12*f6220f1aSBin Meng ('D'<<24)) 13*f6220f1aSBin Meng 14*f6220f1aSBin Meng __packed struct mrc_data_container { 15*f6220f1aSBin Meng u32 signature; /* "MRCD" */ 16*f6220f1aSBin Meng u32 data_size; /* Size of the 'data' field */ 17*f6220f1aSBin Meng u32 checksum; /* IP style checksum */ 18*f6220f1aSBin Meng u32 reserved; /* For header alignment */ 19*f6220f1aSBin Meng u8 data[0]; /* Variable size, platform/run time dependent */ 20*f6220f1aSBin Meng }; 21*f6220f1aSBin Meng 22*f6220f1aSBin Meng struct fmap_entry; 23*f6220f1aSBin Meng struct udevice; 24*f6220f1aSBin Meng 25*f6220f1aSBin Meng /** 26*f6220f1aSBin Meng * mrccache_find_current() - find the latest MRC cache record 27*f6220f1aSBin Meng * 28*f6220f1aSBin Meng * This searches the MRC cache region looking for the latest record to use 29*f6220f1aSBin Meng * for setting up SDRAM 30*f6220f1aSBin Meng * 31*f6220f1aSBin Meng * @entry: Information about the position and size of the MRC cache 32*f6220f1aSBin Meng * @return pointer to latest record, or NULL if none 33*f6220f1aSBin Meng */ 34*f6220f1aSBin Meng struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry); 35*f6220f1aSBin Meng 36*f6220f1aSBin Meng /** 37*f6220f1aSBin Meng * mrccache_update() - update the MRC cache with a new record 38*f6220f1aSBin Meng * 39*f6220f1aSBin Meng * This writes a new record to the end of the MRC cache. If the new record is 40*f6220f1aSBin Meng * the same as the latest record then the write is skipped 41*f6220f1aSBin Meng * 42*f6220f1aSBin Meng * @sf: SPI flash to write to 43*f6220f1aSBin Meng * @entry: Position and size of MRC cache in SPI flash 44*f6220f1aSBin Meng * @cur: Record to write 45*f6220f1aSBin Meng * @return 0 if updated, -EEXIST if the record is the same as the latest 46*f6220f1aSBin Meng * record, other error if SPI write failed 47*f6220f1aSBin Meng */ 48*f6220f1aSBin Meng int mrccache_update(struct udevice *sf, struct fmap_entry *entry, 49*f6220f1aSBin Meng struct mrc_data_container *cur); 50*f6220f1aSBin Meng 51*f6220f1aSBin Meng #endif 52