1 /* 2 * From Coreboot file of same name 3 * 4 * Copyright (C) 2014 Google, Inc 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #ifndef _ARCH_ASM_LAPIC_H 10 #define _ARCH_ASM_LAPIC_H 11 12 #include <asm/io.h> 13 #include <asm/lapic_def.h> 14 #include <asm/msr.h> 15 #include <asm/processor.h> 16 17 /* See if I need to initialize the local apic */ 18 #if CONFIG_SMP || CONFIG_IOAPIC 19 # define NEED_LAPIC 1 20 #else 21 # define NEED_LAPIC 0 22 #endif 23 24 static inline __attribute__((always_inline)) 25 unsigned long lapic_read(unsigned long reg) 26 { 27 return readl(LAPIC_DEFAULT_BASE + reg); 28 } 29 30 static inline __attribute__((always_inline)) 31 void lapic_write(unsigned long reg, unsigned long val) 32 { 33 writel(val, LAPIC_DEFAULT_BASE + reg); 34 } 35 36 static inline __attribute__((always_inline)) void lapic_wait_icr_idle(void) 37 { 38 do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY); 39 } 40 41 static inline void enable_lapic(void) 42 { 43 msr_t msr; 44 45 msr = msr_read(LAPIC_BASE_MSR); 46 msr.hi &= 0xffffff00; 47 msr.lo |= LAPIC_BASE_MSR_ENABLE; 48 msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK; 49 msr.lo |= LAPIC_DEFAULT_BASE; 50 msr_write(LAPIC_BASE_MSR, msr); 51 } 52 53 static inline void disable_lapic(void) 54 { 55 msr_t msr; 56 57 msr = msr_read(LAPIC_BASE_MSR); 58 msr.lo &= ~(1 << 11); 59 msr_write(LAPIC_BASE_MSR, msr); 60 } 61 62 static inline __attribute__((always_inline)) unsigned long lapicid(void) 63 { 64 return lapic_read(LAPIC_ID) >> 24; 65 } 66 67 #if !CONFIG_AP_IN_SIPI_WAIT 68 /* If we need to go back to sipi wait, we use the long non-inlined version of 69 * this function in lapic_cpu_init.c 70 */ 71 static inline __attribute__((always_inline)) void stop_this_cpu(void) 72 { 73 /* Called by an AP when it is ready to halt and wait for a new task */ 74 for (;;) 75 cpu_hlt(); 76 } 77 #else 78 void stop_this_cpu(void); 79 #endif 80 81 #define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \ 82 sizeof(*(ptr)))) 83 84 struct __xchg_dummy { unsigned long a[100]; }; 85 #define __xg(x) ((struct __xchg_dummy *)(x)) 86 87 /* 88 * Note: no "lock" prefix even on SMP: xchg always implies lock anyway 89 * Note 2: xchg has side effect, so that attribute volatile is necessary, 90 * but generally the primitive is invalid, *ptr is output argument. --ANK 91 */ 92 static inline unsigned long __xchg(unsigned long x, volatile void *ptr, 93 int size) 94 { 95 switch (size) { 96 case 1: 97 __asm__ __volatile__("xchgb %b0,%1" 98 : "=q" (x) 99 : "m" (*__xg(ptr)), "0" (x) 100 : "memory"); 101 break; 102 case 2: 103 __asm__ __volatile__("xchgw %w0,%1" 104 : "=r" (x) 105 : "m" (*__xg(ptr)), "0" (x) 106 : "memory"); 107 break; 108 case 4: 109 __asm__ __volatile__("xchgl %0,%1" 110 : "=r" (x) 111 : "m" (*__xg(ptr)), "0" (x) 112 : "memory"); 113 break; 114 } 115 116 return x; 117 } 118 119 static inline void lapic_write_atomic(unsigned long reg, unsigned long v) 120 { 121 (void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE + reg), v); 122 } 123 124 125 #ifdef X86_GOOD_APIC 126 # define FORCE_READ_AROUND_WRITE 0 127 # define lapic_read_around(x) lapic_read(x) 128 # define lapic_write_around(x, y) lapic_write((x), (y)) 129 #else 130 # define FORCE_READ_AROUND_WRITE 1 131 # define lapic_read_around(x) lapic_read(x) 132 # define lapic_write_around(x, y) lapic_write_atomic((x), (y)) 133 #endif 134 135 static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue) 136 { 137 int timeout; 138 unsigned long status; 139 int result; 140 lapic_wait_icr_idle(); 141 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); 142 lapic_write_around(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4)); 143 timeout = 0; 144 do { 145 status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK; 146 } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000); 147 148 result = -1; 149 if (status == LAPIC_ICR_RR_VALID) { 150 *pvalue = lapic_read(LAPIC_RRR); 151 result = 0; 152 } 153 return result; 154 } 155 156 157 void lapic_setup(void); 158 159 #if CONFIG_SMP 160 struct device; 161 int start_cpu(struct device *cpu); 162 #endif /* CONFIG_SMP */ 163 164 int boot_cpu(void); 165 166 /** 167 * struct x86_cpu_priv - Information about a single CPU 168 * 169 * @apic_id: Advanced Programmable Interrupt Controller Identifier, which is 170 * just a number representing the CPU core 171 * 172 * TODO: Move this to driver model once lifecycle is understood 173 */ 174 struct x86_cpu_priv { 175 int apic_id; 176 int start_err; 177 }; 178 179 #endif 180