1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 4 */ 5 6 #ifndef _ARCH_IRQ_H_ 7 #define _ARCH_IRQ_H_ 8 9 #include <dt-bindings/interrupt-router/intel-irq.h> 10 11 /** 12 * Intel interrupt router configuration mechanism 13 * 14 * There are two known ways of Intel interrupt router configuration mechanism 15 * so far. On most cases, the IRQ routing configuraiton is controlled by PCI 16 * configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0). 17 * On some newer platforms like BayTrail and Braswell, the IRQ routing is now 18 * in the IBASE register block where IBASE is memory-mapped. 19 */ 20 enum pirq_config { 21 PIRQ_VIA_PCI, 22 PIRQ_VIA_IBASE 23 }; 24 25 /** 26 * Intel interrupt router control block 27 * 28 * Its members' value will be filled in based on device tree's input. 29 * 30 * @config: PIRQ_VIA_PCI or PIRQ_VIA_IBASE 31 * @link_base: link value base number 32 * @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means 33 * IRQ N is available to be routed 34 * @lb_bdf: irq router's PCI bus/device/function number encoding 35 * @ibase: IBASE register block base address 36 * @actl_8bit: ACTL register width is 8-bit (for ICH series chipset) 37 * @actl_addr: ACTL register offset 38 */ 39 struct irq_router { 40 int config; 41 u32 link_base; 42 u16 irq_mask; 43 u32 bdf; 44 u32 ibase; 45 bool actl_8bit; 46 int actl_addr; 47 }; 48 49 struct pirq_routing { 50 int bdf; 51 int pin; 52 int pirq; 53 }; 54 55 /* PIRQ link number and value conversion */ 56 #define LINK_V2N(link, base) (link - base) 57 #define LINK_N2V(link, base) (link + base) 58 59 #define PIRQ_BITMAP 0xdef8 60 61 /** 62 * irq_router_common_init() - Perform common x86 interrupt init 63 * 64 * This creates the PIRQ routing table and routes the IRQs 65 */ 66 int irq_router_common_init(struct udevice *dev); 67 68 #endif /* _ARCH_IRQ_H_ */ 69