1*a2f5d091SSimon Glass /* 2*a2f5d091SSimon Glass * From coreboot file of the same name 3*a2f5d091SSimon Glass * 4*a2f5d091SSimon Glass * Copyright (C) 2010 coresystems GmbH 5*a2f5d091SSimon Glass * 6*a2f5d091SSimon Glass * SPDX-License-Identifier: GPL-2.0 7*a2f5d091SSimon Glass */ 8*a2f5d091SSimon Glass 9*a2f5d091SSimon Glass #ifndef __ASM_IOAPIC_H 10*a2f5d091SSimon Glass #define __ASM_IOAPIC_H 11*a2f5d091SSimon Glass 12*a2f5d091SSimon Glass #define IO_APIC_ADDR 0xfec00000 13*a2f5d091SSimon Glass #define IO_APIC_INDEX IO_APIC_ADDR 14*a2f5d091SSimon Glass #define IO_APIC_DATA (IO_APIC_ADDR + 0x10) 15*a2f5d091SSimon Glass #define IO_APIC_INTERRUPTS 24 16*a2f5d091SSimon Glass 17*a2f5d091SSimon Glass #define ALL (0xff << 24) 18*a2f5d091SSimon Glass #define NONE 0 19*a2f5d091SSimon Glass #define DISABLED (1 << 16) 20*a2f5d091SSimon Glass #define ENABLED (0 << 16) 21*a2f5d091SSimon Glass #define TRIGGER_EDGE (0 << 15) 22*a2f5d091SSimon Glass #define TRIGGER_LEVEL (1 << 15) 23*a2f5d091SSimon Glass #define POLARITY_HIGH (0 << 13) 24*a2f5d091SSimon Glass #define POLARITY_LOW (1 << 13) 25*a2f5d091SSimon Glass #define PHYSICAL_DEST (0 << 11) 26*a2f5d091SSimon Glass #define LOGICAL_DEST (1 << 11) 27*a2f5d091SSimon Glass #define ExtINT (7 << 8) 28*a2f5d091SSimon Glass #define NMI (4 << 8) 29*a2f5d091SSimon Glass #define SMI (2 << 8) 30*a2f5d091SSimon Glass #define INT (1 << 8) 31*a2f5d091SSimon Glass 32*a2f5d091SSimon Glass u32 io_apic_read(u32 ioapic_base, u32 reg); 33*a2f5d091SSimon Glass void io_apic_write(u32 ioapic_base, u32 reg, u32 value); 34*a2f5d091SSimon Glass void set_ioapic_id(u32 ioapic_base, u8 ioapic_id); 35*a2f5d091SSimon Glass void setup_ioapic(u32 ioapic_base, u8 ioapic_id); 36*a2f5d091SSimon Glass void clear_ioapic(u32 ioapic_base); 37*a2f5d091SSimon Glass 38*a2f5d091SSimon Glass #endif 39