1fea25720SGraeme Russ /* 2fea25720SGraeme Russ * (C) Copyright 2009 3fea25720SGraeme Russ * Graeme Russ, graeme.russ@gmail.com 4fea25720SGraeme Russ * 5fea25720SGraeme Russ * (C) Copyright 2002 6fa82f871SAlbert ARIBAUD * Daniel Engström, Omicron Ceti AB, daniel@omicron.se 7fea25720SGraeme Russ * 81a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 9fea25720SGraeme Russ */ 10fea25720SGraeme Russ 11fea25720SGraeme Russ #ifndef __ASM_INTERRUPT_H_ 12fea25720SGraeme Russ #define __ASM_INTERRUPT_H_ 1 13fea25720SGraeme Russ 14fea25720SGraeme Russ #include <asm/types.h> 15fea25720SGraeme Russ 16fea25720SGraeme Russ /* arch/x86/cpu/interrupts.c */ 17fea25720SGraeme Russ void set_vector(u8 intnum, void *routine); 18fea25720SGraeme Russ 1916263087SMike Williams /* arch/x86/lib/interrupts.c */ 20fea25720SGraeme Russ void disable_irq(int irq); 21fea25720SGraeme Russ void enable_irq(int irq); 22fea25720SGraeme Russ 23fea25720SGraeme Russ /* Architecture specific functions */ 24fea25720SGraeme Russ void mask_irq(int irq); 25fea25720SGraeme Russ void unmask_irq(int irq); 26fea25720SGraeme Russ void specific_eoi(int irq); 27fea25720SGraeme Russ 28fea25720SGraeme Russ extern char exception_stack[]; 29fea25720SGraeme Russ 30*a0bd851eSSimon Glass /** 31*a0bd851eSSimon Glass * configure_irq_trigger() - Configure IRQ triggering 32*a0bd851eSSimon Glass * 33*a0bd851eSSimon Glass * Switch the given interrupt to be level / edge triggered 34*a0bd851eSSimon Glass * 35*a0bd851eSSimon Glass * @param int_num legacy interrupt number (3-7, 9-15) 36*a0bd851eSSimon Glass * @param is_level_triggered true for level triggered interrupt, false for 37*a0bd851eSSimon Glass * edge triggered interrupt 38*a0bd851eSSimon Glass */ 39*a0bd851eSSimon Glass void configure_irq_trigger(int int_num, bool is_level_triggered); 40*a0bd851eSSimon Glass 41fea25720SGraeme Russ #endif 42