1fea25720SGraeme Russ /* 2fea25720SGraeme Russ * (C) Copyright 2009 3fea25720SGraeme Russ * Graeme Russ, graeme.russ@gmail.com 4fea25720SGraeme Russ * 5fea25720SGraeme Russ * (C) Copyright 2002 6fa82f871SAlbert ARIBAUD * Daniel Engström, Omicron Ceti AB, daniel@omicron.se 7fea25720SGraeme Russ * 81a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 9fea25720SGraeme Russ */ 10fea25720SGraeme Russ 11fea25720SGraeme Russ #ifndef __ASM_INTERRUPT_H_ 12fea25720SGraeme Russ #define __ASM_INTERRUPT_H_ 1 13fea25720SGraeme Russ 14fea25720SGraeme Russ #include <asm/types.h> 15fea25720SGraeme Russ 16*013cf483SBin Meng /* Architecture defined exceptions */ 17*013cf483SBin Meng enum x86_exception { 18*013cf483SBin Meng EXC_DE = 0, 19*013cf483SBin Meng EXC_DB, 20*013cf483SBin Meng EXC_NMI, 21*013cf483SBin Meng EXC_BP, 22*013cf483SBin Meng EXC_OF, 23*013cf483SBin Meng EXC_BR, 24*013cf483SBin Meng EXC_UD, 25*013cf483SBin Meng EXC_NM, 26*013cf483SBin Meng EXC_DF, 27*013cf483SBin Meng EXC_CSO, 28*013cf483SBin Meng EXC_TS, 29*013cf483SBin Meng EXC_NP, 30*013cf483SBin Meng EXC_SS, 31*013cf483SBin Meng EXC_GP, 32*013cf483SBin Meng EXC_PF, 33*013cf483SBin Meng EXC_MF = 16, 34*013cf483SBin Meng EXC_AC, 35*013cf483SBin Meng EXC_MC, 36*013cf483SBin Meng EXC_XM, 37*013cf483SBin Meng EXC_VE 38*013cf483SBin Meng }; 39*013cf483SBin Meng 40fea25720SGraeme Russ /* arch/x86/cpu/interrupts.c */ 41fea25720SGraeme Russ void set_vector(u8 intnum, void *routine); 42fea25720SGraeme Russ 43fea25720SGraeme Russ /* Architecture specific functions */ 44fea25720SGraeme Russ void mask_irq(int irq); 45fea25720SGraeme Russ void unmask_irq(int irq); 46fea25720SGraeme Russ void specific_eoi(int irq); 47fea25720SGraeme Russ 48fea25720SGraeme Russ extern char exception_stack[]; 49fea25720SGraeme Russ 50a0bd851eSSimon Glass /** 51a0bd851eSSimon Glass * configure_irq_trigger() - Configure IRQ triggering 52a0bd851eSSimon Glass * 53a0bd851eSSimon Glass * Switch the given interrupt to be level / edge triggered 54a0bd851eSSimon Glass * 55a0bd851eSSimon Glass * @param int_num legacy interrupt number (3-7, 9-15) 56a0bd851eSSimon Glass * @param is_level_triggered true for level triggered interrupt, false for 57a0bd851eSSimon Glass * edge triggered interrupt 58a0bd851eSSimon Glass */ 59a0bd851eSSimon Glass void configure_irq_trigger(int int_num, bool is_level_triggered); 60a0bd851eSSimon Glass 616f41e0e7SSimon Glass void *x86_get_idt(void); 626f41e0e7SSimon Glass 63fea25720SGraeme Russ #endif 64