xref: /openbmc/u-boot/arch/x86/include/asm/intel_regs.h (revision 50dd3da0)
106d336ccSSimon Glass /*
206d336ccSSimon Glass  * Copyright (c) 2016 Google, Inc
306d336ccSSimon Glass  *
406d336ccSSimon Glass  * SPDX-License-Identifier:	GPL-2.0
506d336ccSSimon Glass  */
606d336ccSSimon Glass 
706d336ccSSimon Glass #ifndef __ASM_INTEL_REGS_H
806d336ccSSimon Glass #define __ASM_INTEL_REGS_H
906d336ccSSimon Glass 
1006d336ccSSimon Glass /* Access the memory-controller hub */
1106d336ccSSimon Glass #define MCH_BASE_ADDRESS	0xfed10000
1206d336ccSSimon Glass #define MCH_BASE_SIZE		0x8000
1306d336ccSSimon Glass #define MCHBAR_REG(reg)		(MCH_BASE_ADDRESS + (reg))
1406d336ccSSimon Glass 
15*50dd3da0SSimon Glass #define MCHBAR_PEI_VERSION	0x5034
16*50dd3da0SSimon Glass #define MCH_PKG_POWER_LIMIT_LO	0x59a0
17*50dd3da0SSimon Glass #define MCH_PKG_POWER_LIMIT_HI	0x59a4
18*50dd3da0SSimon Glass #define MCH_DDR_POWER_LIMIT_LO	0x58e0
19*50dd3da0SSimon Glass #define MCH_DDR_POWER_LIMIT_HI	0x58e4
20*50dd3da0SSimon Glass 
21bb096b9fSSimon Glass /* Access the Root Complex Register Block */
22bb096b9fSSimon Glass #define RCB_BASE_ADDRESS	0xfed1c000
23bb096b9fSSimon Glass #define RCB_REG(reg)		(RCB_BASE_ADDRESS + (reg))
24bb096b9fSSimon Glass 
25*50dd3da0SSimon Glass #define SOFT_RESET_CTRL		0x38f4
26*50dd3da0SSimon Glass #define SOFT_RESET_DATA		0x38f8
27*50dd3da0SSimon Glass 
2806d336ccSSimon Glass #endif
29