1*83d290c5STom Rini /* SPDX-License-Identifier: Intel */ 2abddcd52SBin Meng /* 3abddcd52SBin Meng * Copyright (C) 2013, Intel Corporation 4abddcd52SBin Meng * Copyright (C) 2015, Google, Inc 5abddcd52SBin Meng */ 6abddcd52SBin Meng 7abddcd52SBin Meng #ifndef _FSP_AZALIA_H_ 8abddcd52SBin Meng #define _FSP_AZALIA_H_ 9abddcd52SBin Meng 10abddcd52SBin Meng struct __packed azalia_verb_table_header { 11abddcd52SBin Meng u32 vendor_device_id; 12abddcd52SBin Meng u16 sub_system_id; 13abddcd52SBin Meng u8 revision_id; /* 0xff applies to all steppings */ 14abddcd52SBin Meng u8 front_panel_support; 15abddcd52SBin Meng u16 number_of_rear_jacks; 16abddcd52SBin Meng u16 number_of_front_jacks; 17abddcd52SBin Meng }; 18abddcd52SBin Meng 19abddcd52SBin Meng struct __packed azalia_verb_table { 20abddcd52SBin Meng struct azalia_verb_table_header header; 21abddcd52SBin Meng const u32 *data; 22abddcd52SBin Meng }; 23abddcd52SBin Meng 24abddcd52SBin Meng struct __packed azalia_config { 25abddcd52SBin Meng u8 pme_enable:1; 26abddcd52SBin Meng u8 docking_supported:1; 27abddcd52SBin Meng u8 docking_attached:1; 28abddcd52SBin Meng u8 hdmi_codec_enable:1; 29abddcd52SBin Meng u8 azalia_v_ci_enable:1; 30abddcd52SBin Meng u8 rsvdbits:3; 31abddcd52SBin Meng /* number of verb tables provided by platform */ 32abddcd52SBin Meng u8 verb_table_num; 33abddcd52SBin Meng const struct azalia_verb_table *verb_table; 34abddcd52SBin Meng /* delay timer after azalia reset */ 35abddcd52SBin Meng u16 reset_wait_timer_ms; 36abddcd52SBin Meng }; 37abddcd52SBin Meng 38abddcd52SBin Meng #endif 39