1*abddcd52SBin Meng /* 2*abddcd52SBin Meng * Copyright (C) 2013, Intel Corporation 3*abddcd52SBin Meng * Copyright (C) 2015, Google, Inc 4*abddcd52SBin Meng * 5*abddcd52SBin Meng * SPDX-License-Identifier: Intel 6*abddcd52SBin Meng */ 7*abddcd52SBin Meng 8*abddcd52SBin Meng #ifndef _FSP_AZALIA_H_ 9*abddcd52SBin Meng #define _FSP_AZALIA_H_ 10*abddcd52SBin Meng 11*abddcd52SBin Meng struct __packed azalia_verb_table_header { 12*abddcd52SBin Meng u32 vendor_device_id; 13*abddcd52SBin Meng u16 sub_system_id; 14*abddcd52SBin Meng u8 revision_id; /* 0xff applies to all steppings */ 15*abddcd52SBin Meng u8 front_panel_support; 16*abddcd52SBin Meng u16 number_of_rear_jacks; 17*abddcd52SBin Meng u16 number_of_front_jacks; 18*abddcd52SBin Meng }; 19*abddcd52SBin Meng 20*abddcd52SBin Meng struct __packed azalia_verb_table { 21*abddcd52SBin Meng struct azalia_verb_table_header header; 22*abddcd52SBin Meng const u32 *data; 23*abddcd52SBin Meng }; 24*abddcd52SBin Meng 25*abddcd52SBin Meng struct __packed azalia_config { 26*abddcd52SBin Meng u8 pme_enable:1; 27*abddcd52SBin Meng u8 docking_supported:1; 28*abddcd52SBin Meng u8 docking_attached:1; 29*abddcd52SBin Meng u8 hdmi_codec_enable:1; 30*abddcd52SBin Meng u8 azalia_v_ci_enable:1; 31*abddcd52SBin Meng u8 rsvdbits:3; 32*abddcd52SBin Meng /* number of verb tables provided by platform */ 33*abddcd52SBin Meng u8 verb_table_num; 34*abddcd52SBin Meng const struct azalia_verb_table *verb_table; 35*abddcd52SBin Meng /* delay timer after azalia reset */ 36*abddcd52SBin Meng u16 reset_wait_timer_ms; 37*abddcd52SBin Meng }; 38*abddcd52SBin Meng 39*abddcd52SBin Meng #endif 40