1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 250dd3da0SSimon Glass /* 350dd3da0SSimon Glass * Copyright (c) 2016 Google, Inc 450dd3da0SSimon Glass */ 550dd3da0SSimon Glass 650dd3da0SSimon Glass #ifndef __ASM_CPU_COMMON_H 750dd3da0SSimon Glass #define __ASM_CPU_COMMON_H 850dd3da0SSimon Glass 950dd3da0SSimon Glass #define IA32_PERF_CTL 0x199 1050dd3da0SSimon Glass 1150dd3da0SSimon Glass /** 1250dd3da0SSimon Glass * cpu_common_init() - Set up common CPU init 1350dd3da0SSimon Glass * 1450dd3da0SSimon Glass * This reports BIST failure, enables the LAPIC, updates microcode, enables 1550dd3da0SSimon Glass * the upper 128-bytes of CROM RAM, probes the northbridge, PCH, LPC and SATA. 1650dd3da0SSimon Glass * 1750dd3da0SSimon Glass * @return 0 if OK, -ve on error 1850dd3da0SSimon Glass */ 1950dd3da0SSimon Glass int cpu_common_init(void); 2050dd3da0SSimon Glass 2150dd3da0SSimon Glass /** 2250dd3da0SSimon Glass * cpu_set_flex_ratio_to_tdp_nominal() - Set up the maximum non-turbo rate 2350dd3da0SSimon Glass * 2450dd3da0SSimon Glass * If a change is needed, this function will do a soft reset so it takes 2550dd3da0SSimon Glass * effect. 2650dd3da0SSimon Glass * 2750dd3da0SSimon Glass * Some details are available here: 2850dd3da0SSimon Glass * http://forum.hwbot.org/showthread.php?t=76092 2950dd3da0SSimon Glass * 3050dd3da0SSimon Glass * @return 0 if OK, -ve on error 3150dd3da0SSimon Glass */ 3250dd3da0SSimon Glass int cpu_set_flex_ratio_to_tdp_nominal(void); 3350dd3da0SSimon Glass 3450dd3da0SSimon Glass #endif 35