1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> 4 */ 5 6 #ifndef __CMOS_LAYOUT_H 7 #define __CMOS_LAYOUT_H 8 9 /* 10 * The RTC internal registers and RAM is organized as two banks of 128 bytes 11 * each, called the standard and extended banks. The first 14 bytes of the 12 * standard bank contain the RTC time and date information along with four 13 * registers, A - D, that are used for configuration of the RTC. The extended 14 * bank contains a full 128 bytes of battery backed SRAM. 15 * 16 * For simplicity in U-Boot we only support CMOS in the standard bank, and 17 * its base address starts from offset 0x10, which leaves us 112 bytes space. 18 */ 19 #define CMOS_BASE 0x10 20 21 /* 22 * The file records all offsets off CMOS_BASE that is currently used by 23 * U-Boot for various reasons. It is put in such a unified place in order 24 * to be consistent across platforms. 25 */ 26 27 /* stack address for S3 boot in a FSP configuration, 4 bytes */ 28 #define CMOS_FSP_STACK_ADDR CMOS_BASE 29 30 #endif /* __CMOS_LAYOUT_H */ 31