1 /*
2  * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __CMOS_LAYOUT_H
8 #define __CMOS_LAYOUT_H
9 
10 /*
11  * The RTC internal registers and RAM is organized as two banks of 128 bytes
12  * each, called the standard and extended banks. The first 14 bytes of the
13  * standard bank contain the RTC time and date information along with four
14  * registers, A - D, that are used for configuration of the RTC. The extended
15  * bank contains a full 128 bytes of battery backed SRAM.
16  *
17  * For simplicity in U-Boot we only support CMOS in the standard bank, and
18  * its base address starts from offset 0x10, which leaves us 112 bytes space.
19  */
20 #define CMOS_BASE		0x10
21 
22 /*
23  * The file records all offsets off CMOS_BASE that is currently used by
24  * U-Boot for various reasons. It is put in such a unified place in order
25  * to be consistent across platforms.
26  */
27 
28 /* stack address for S3 boot in a FSP configuration, 4 bytes */
29 #define CMOS_FSP_STACK_ADDR	CMOS_BASE
30 
31 #endif /* __CMOS_LAYOUT_H */
32