1*ba65808eSBin Meng /* 2*ba65808eSBin Meng * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> 3*ba65808eSBin Meng * 4*ba65808eSBin Meng * SPDX-License-Identifier: GPL-2.0+ 5*ba65808eSBin Meng */ 6*ba65808eSBin Meng 7*ba65808eSBin Meng #ifndef __CMOS_LAYOUT_H 8*ba65808eSBin Meng #define __CMOS_LAYOUT_H 9*ba65808eSBin Meng 10*ba65808eSBin Meng /* 11*ba65808eSBin Meng * The RTC internal registers and RAM is organized as two banks of 128 bytes 12*ba65808eSBin Meng * each, called the standard and extended banks. The first 14 bytes of the 13*ba65808eSBin Meng * standard bank contain the RTC time and date information along with four 14*ba65808eSBin Meng * registers, A - D, that are used for configuration of the RTC. The extended 15*ba65808eSBin Meng * bank contains a full 128 bytes of battery backed SRAM. 16*ba65808eSBin Meng * 17*ba65808eSBin Meng * For simplicity in U-Boot we only support CMOS in the standard bank, and 18*ba65808eSBin Meng * its base address starts from offset 0x10, which leaves us 112 bytes space. 19*ba65808eSBin Meng */ 20*ba65808eSBin Meng #define CMOS_BASE 0x10 21*ba65808eSBin Meng 22*ba65808eSBin Meng /* 23*ba65808eSBin Meng * The file records all offsets off CMOS_BASE that is currently used by 24*ba65808eSBin Meng * U-Boot for various reasons. It is put in such a unified place in order 25*ba65808eSBin Meng * to be consistent across platforms. 26*ba65808eSBin Meng */ 27*ba65808eSBin Meng 28*ba65808eSBin Meng /* stack address for S3 boot in a FSP configuration, 4 bytes */ 29*ba65808eSBin Meng #define CMOS_FSP_STACK_ADDR CMOS_BASE 30*ba65808eSBin Meng 31*ba65808eSBin Meng #endif /* __CMOS_LAYOUT_H */ 32