1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __X86_CACHE_H__ 8 #define __X86_CACHE_H__ 9 10 /* 11 * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise 12 * use 64-bytes, a safe default for x86. 13 */ 14 #ifndef CONFIG_SYS_CACHELINE_SIZE 15 #define CONFIG_SYS_CACHELINE_SIZE 64 16 #endif 17 18 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 19 20 static inline void wbinvd(void) 21 { 22 asm volatile ("wbinvd" : : : "memory"); 23 } 24 25 static inline void invd(void) 26 { 27 asm volatile("invd" : : : "memory"); 28 } 29 30 /* Enable caches and write buffer */ 31 void enable_caches(void); 32 33 /* Disable caches and write buffer */ 34 void disable_caches(void); 35 36 #endif /* __X86_CACHE_H__ */ 37