13620f860SAnton Staaf /* 23620f860SAnton Staaf * Copyright (c) 2011 The Chromium OS Authors. 33620f860SAnton Staaf * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 53620f860SAnton Staaf */ 63620f860SAnton Staaf 73620f860SAnton Staaf #ifndef __X86_CACHE_H__ 83620f860SAnton Staaf #define __X86_CACHE_H__ 93620f860SAnton Staaf 103620f860SAnton Staaf /* 113620f860SAnton Staaf * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise 123620f860SAnton Staaf * use 64-bytes, a safe default for x86. 133620f860SAnton Staaf */ 14*bf4ea7edSStefan Roese #ifndef CONFIG_SYS_CACHELINE_SIZE 15*bf4ea7edSStefan Roese #define CONFIG_SYS_CACHELINE_SIZE 64 163620f860SAnton Staaf #endif 173620f860SAnton Staaf 18*bf4ea7edSStefan Roese #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE 19*bf4ea7edSStefan Roese 20095593c0SStefan Reinauer static inline void wbinvd(void) 21095593c0SStefan Reinauer { 22095593c0SStefan Reinauer asm volatile ("wbinvd" : : : "memory"); 23095593c0SStefan Reinauer } 24095593c0SStefan Reinauer 25095593c0SStefan Reinauer static inline void invd(void) 26095593c0SStefan Reinauer { 27095593c0SStefan Reinauer asm volatile("invd" : : : "memory"); 28095593c0SStefan Reinauer } 29095593c0SStefan Reinauer 30095593c0SStefan Reinauer /* Enable caches and write buffer */ 31095593c0SStefan Reinauer void enable_caches(void); 32095593c0SStefan Reinauer 33095593c0SStefan Reinauer /* Disable caches and write buffer */ 34095593c0SStefan Reinauer void disable_caches(void); 35095593c0SStefan Reinauer 363620f860SAnton Staaf #endif /* __X86_CACHE_H__ */ 37