1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (c) 2017 Intel Corporation 4 * 5 * Partially based on southcluster.asl for other x86 platforms 6 */ 7 8Device (PCI0) 9{ 10 Name (_HID, EISAID("PNP0A08")) /* PCIe */ 11 Name (_CID, EISAID("PNP0A03")) /* PCI */ 12 13 Name (_ADR, 0) 14 Name (_BBN, 0) 15 16 Name (MCRS, ResourceTemplate() 17 { 18 /* Bus Numbers */ 19 WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode, 20 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00) 21 22 /* IO Region 0 */ 23 WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 24 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00) 25 26 /* PCI Config Space */ 27 IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) 28 29 /* IO Region 1 */ 30 WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 31 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01) 32 33 /* GPIO Low Memory Region */ 34 DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, 35 Cacheable, ReadWrite, 36 0x00000000, 0x000ddcc0, 0x000ddccf, 0x00000000, 37 0x00000010, , , GP00) 38 39 /* PSH Memory Region 0 */ 40 DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, 41 Cacheable, ReadWrite, 42 0x00000000, 0x04819000, 0x04898fff, 0x00000000, 43 0x00080000, , , PSH0) 44 45 /* PSH Memory Region 1 */ 46 DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, 47 Cacheable, ReadWrite, 48 0x00000000, 0x04919000, 0x04920fff, 0x00000000, 49 0x00008000, , , PSH1) 50 51 /* SST Memory Region */ 52 DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, 53 Cacheable, ReadWrite, 54 0x00000000, 0x05e00000, 0x05ffffff, 0x00000000, 55 0x00200000, , , SST0) 56 57 /* PCI Memory Region */ 58 DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, 59 Cacheable, ReadWrite, 60 0x00000000, 0x80000000, 0xffffffff, 0x00000000, 61 0x80000000, , , PMEM) 62 }) 63 64 Method (_CRS, 0, Serialized) 65 { 66 Return (MCRS) 67 } 68 69 Method (_OSC, 4) 70 { 71 /* Check for proper GUID */ 72 If (LEqual(Arg0, ToUUID("33db4d5b-1ff7-401c-9657-7441c03dd766"))) { 73 /* Let OS control everything */ 74 Return (Arg3) 75 } Else { 76 /* Unrecognized UUID */ 77 CreateDWordField(Arg3, 0, CDW1) 78 Or(CDW1, 4, CDW1) 79 Return (Arg3) 80 } 81 } 82 83 Device (SDHC) 84 { 85 Name (_ADR, 0x00010003) 86 Name (_DEP, Package (0x01) 87 { 88 GPIO 89 }) 90 Name (PSTS, Zero) 91 92 Method (_STA) 93 { 94 Return (STA_VISIBLE) 95 } 96 97 Method (_PS3, 0, NotSerialized) 98 { 99 } 100 101 Method (_PS0, 0, NotSerialized) 102 { 103 If (PSTS == Zero) 104 { 105 If (^^GPIO.AVBL == One) 106 { 107 ^^GPIO.WFD3 = One 108 PSTS = One 109 } 110 } 111 } 112 113 /* BCM43340 */ 114 Device (BRC1) 115 { 116 Name (_ADR, 0x01) 117 Name (_DEP, Package (0x01) 118 { 119 GPIO 120 }) 121 122 Method (_STA) 123 { 124 Return (STA_VISIBLE) 125 } 126 127 Method (_RMV, 0, NotSerialized) 128 { 129 Return (Zero) 130 } 131 132 Method (_PS3, 0, NotSerialized) 133 { 134 If (^^^GPIO.AVBL == One) 135 { 136 ^^^GPIO.WFD3 = Zero 137 PSTS = Zero 138 } 139 } 140 141 Method (_PS0, 0, NotSerialized) 142 { 143 If (PSTS == Zero) 144 { 145 If (^^^GPIO.AVBL == One) 146 { 147 ^^^GPIO.WFD3 = One 148 PSTS = One 149 } 150 } 151 } 152 } 153 154 Device (BRC2) 155 { 156 Name (_ADR, 0x02) 157 Method (_STA, 0, NotSerialized) 158 { 159 Return (STA_VISIBLE) 160 } 161 162 Method (_RMV, 0, NotSerialized) 163 { 164 Return (Zero) 165 } 166 } 167 } 168 169 Device (SPI5) 170 { 171 Name (_ADR, 0x00070001) 172 Name (RBUF, ResourceTemplate() 173 { 174 GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly, 175 "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 110 } 176 GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly, 177 "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 111 } 178 GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly, 179 "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 112 } 180 GpioIo(Exclusive, PullUp, 0, 0, IoRestrictionOutputOnly, 181 "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 113 } 182 183 FixedDMA(0x000d, 0x0002, Width32bit, ) 184 FixedDMA(0x000c, 0x0003, Width32bit, ) 185 }) 186 187 Method (_CRS, 0, NotSerialized) 188 { 189 Return (RBUF) 190 } 191 192 /* 193 * See 194 * http://www.kernel.org/doc/Documentation/acpi/gpio-properties.txt 195 * for more information about GPIO bindings. 196 */ 197 Name (_DSD, Package () { 198 ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), 199 Package () { 200 Package () { 201 "cs-gpios", Package () { 202 ^SPI5, 0, 0, 0, 203 ^SPI5, 1, 0, 0, 204 ^SPI5, 2, 0, 0, 205 ^SPI5, 3, 0, 0, 206 }, 207 }, 208 } 209 }) 210 211 Method (_STA, 0, NotSerialized) 212 { 213 Return (STA_VISIBLE) 214 } 215 } 216 217 Device (I2C1) 218 { 219 Name (_ADR, 0x00080000) 220 221 Method (_STA, 0, NotSerialized) 222 { 223 Return (STA_VISIBLE) 224 } 225 } 226 227 Device (I2C6) 228 { 229 Name (_ADR, 0x00090001) 230 231 Method (_STA, 0, NotSerialized) 232 { 233 Return (STA_VISIBLE) 234 } 235 } 236 237 Device (GPIO) 238 { 239 Name (_ADR, 0x000c0000) 240 241 Method (_STA) 242 { 243 Return (STA_VISIBLE) 244 } 245 246 Name (AVBL, Zero) 247 Method (_REG, 2, NotSerialized) 248 { 249 If (Arg0 == 0x08) 250 { 251 AVBL = Arg1 252 } 253 } 254 255 OperationRegion (GPOP, GeneralPurposeIo, 0, 1) 256 Field (GPOP, ByteAcc, NoLock, Preserve) 257 { 258 Connection ( 259 GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, 260 "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 96 } 261 ), 262 WFD3, 1, 263 } 264 } 265 266 Device (PWM0) 267 { 268 Name (_ADR, 0x00170000) 269 270 Method (_STA, 0, NotSerialized) 271 { 272 Return (STA_VISIBLE) 273 } 274 } 275 276 Device (HSU0) 277 { 278 Name (_ADR, 0x00040001) 279 280 Method (_STA, 0, NotSerialized) 281 { 282 Return (STA_VISIBLE) 283 } 284 285 Device (BTH0) 286 { 287 Name (_HID, "BCM2E95") 288 Name (_DEP, Package () 289 { 290 GPIO, 291 HSU0 292 }) 293 294 Method (_STA, 0, NotSerialized) 295 { 296 Return (STA_VISIBLE) 297 } 298 299 Method (_CRS, 0, Serialized) 300 { 301 Name (RBUF, ResourceTemplate() 302 { 303 UartSerialBus(0x0001C200, DataBitsEight, StopBitsOne, 304 0xFC, LittleEndian, ParityTypeNone, FlowControlHardware, 305 0x20, 0x20, "\\_SB.PCI0.HSU0", 0, ResourceConsumer, , ) 306 GpioInt(Level, ActiveHigh, Exclusive, PullNone, 0, 307 "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 185 } 308 GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, 309 "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 184 } 310 GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, 311 "\\_SB.PCI0.GPIO", 0, ResourceConsumer, , ) { 71 } 312 }) 313 Return (RBUF) 314 } 315 316 Name (_DSD, Package () { 317 ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), 318 Package () { 319 Package () { "host-wakeup-gpios", Package () { ^BTH0, 0, 0, 0 } }, 320 Package () { "device-wakeup-gpios", Package () { ^BTH0, 1, 0, 0 } }, 321 Package () { "shutdown-gpios", Package () { ^BTH0, 2, 0, 0 } }, 322 } 323 }) 324 } 325 } 326 327 Device (IPC1) 328 { 329 Name (_ADR, 0x00130000) 330 331 Method (_STA, 0, NotSerialized) 332 { 333 Return (STA_VISIBLE) 334 } 335 336 Device (PMIC) 337 { 338 Name (_ADR, Zero) 339 Name (_HID, "INTC100E") 340 Name (_CID, "INTC100E") 341 Name (_DDN, "Basin Cove PMIC") 342 Name (_DEP, Package () 343 { 344 IPC1 345 }) 346 347 Method (_STA, 0, NotSerialized) 348 { 349 Return (STA_VISIBLE) 350 } 351 352 Method (_CRS, 0, Serialized) 353 { 354 Name (RBUF, ResourceTemplate() 355 { 356 /* 357 * Shadow registers in SRAM for PMIC: 358 * SRAM PMIC register 359 * -------------------- 360 * 0x00- Unknown 361 * 0x03 THRMIRQ (0x04) 362 * 0x04 BCUIRQ (0x05) 363 * 0x05 ADCIRQ (0x06) 364 * 0x06 CHGRIRQ0 (0x07) 365 * 0x07 CHGRIRQ1 (0x08) 366 * 0x08- Unknown 367 * 0x0a PBSTATUS (0x27) 368 * 0x0b- Unknown 369 */ 370 Memory32Fixed(ReadWrite, 0xFFFFF610, 0x00000010) 371 Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 30 } 372 Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 23 } 373 Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 52 } 374 Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 51 } 375 Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 50 } 376 Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 27 } 377 Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, ,, ) { 49 } 378 }) 379 Return (RBUF) 380 } 381 382 OperationRegion (PMOP, 0x8D, Zero, 0x0100) 383 Field (PMOP, DWordAcc, NoLock, Preserve) 384 { 385 SEL1, 32, 386 SEL2, 32, 387 VCCL, 32, 388 VNNL, 32, 389 AONL, 32, 390 CNTC, 32, 391 CNTN, 32, 392 AONN, 32, 393 CNT1, 32, 394 CNT2, 32, 395 CNT3, 32, 396 FLEX, 32, 397 PRG1, 32, 398 PRG2, 32, 399 PRG3, 32, 400 VLDO, 32, 401 } 402 403 Name (AVBL, Zero) 404 Method (_REG, 2, NotSerialized) 405 { 406 If ((Arg0 == 0x8D)) 407 { 408 AVBL = Arg1 409 } 410 } 411 } 412 } 413} 414 415Device (FLIS) 416{ 417 Name (_HID, "INTC1002") 418 Name (_DDN, "Intel Merrifield Family-Level Interface Shim") 419 Name (RBUF, ResourceTemplate() 420 { 421 Memory32Fixed(ReadWrite, 0xFF0C0000, 0x00008000) 422 PinGroup("spi5", ResourceProducer, ) { 90, 91, 92, 93, 94, 95, 96 } 423 PinGroup("uart0", ResourceProducer, ) { 115, 116, 117, 118 } 424 PinGroup("uart1", ResourceProducer, ) { 119, 120, 121, 122 } 425 PinGroup("uart2", ResourceProducer, ) { 123, 124, 125, 126 } 426 PinGroup("pwm0", ResourceProducer, ) { 144 } 427 PinGroup("pwm1", ResourceProducer, ) { 145 } 428 PinGroup("pwm2", ResourceProducer, ) { 132 } 429 PinGroup("pwm3", ResourceProducer, ) { 133 } 430 }) 431 432 Method (_CRS, 0, NotSerialized) 433 { 434 Return (RBUF) 435 } 436 437 Method (_STA, 0, NotSerialized) 438 { 439 Return (STA_VISIBLE) 440 } 441} 442