1adfe3b24SBin Meng /* 2adfe3b24SBin Meng * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 3adfe3b24SBin Meng * 4adfe3b24SBin Meng * SPDX-License-Identifier: GPL-2.0+ 5adfe3b24SBin Meng */ 6adfe3b24SBin Meng 7adfe3b24SBin Meng #ifndef _X86_ARCH_TNC_H_ 8adfe3b24SBin Meng #define _X86_ARCH_TNC_H_ 9adfe3b24SBin Meng 10*afbf1404SBin Meng /* Memory BAR Enable */ 11*afbf1404SBin Meng #define MEM_BAR_EN 0x00000001 12adfe3b24SBin Meng 13*afbf1404SBin Meng /* LPC PCI Configuration Registers */ 14*afbf1404SBin Meng #define LPC_RCBA 0xf0 15*afbf1404SBin Meng 16*afbf1404SBin Meng /* Root Complex Register Block */ 17*afbf1404SBin Meng struct tnc_rcba { 18*afbf1404SBin Meng u32 rctl; 19*afbf1404SBin Meng u32 esd; 20*afbf1404SBin Meng u32 rsvd1[2]; 21*afbf1404SBin Meng u32 hdd; 22*afbf1404SBin Meng u32 rsvd2; 23*afbf1404SBin Meng u32 hdba; 24*afbf1404SBin Meng u32 rsvd3[3129]; 25*afbf1404SBin Meng u32 d31ip; 26*afbf1404SBin Meng u32 rsvd4[3]; 27*afbf1404SBin Meng u32 d27ip; 28*afbf1404SBin Meng u32 rsvd5; 29*afbf1404SBin Meng u32 d02ip; 30*afbf1404SBin Meng u32 rsvd6; 31*afbf1404SBin Meng u32 d26ip; 32*afbf1404SBin Meng u32 d25ip; 33*afbf1404SBin Meng u32 d24ip; 34*afbf1404SBin Meng u32 d23ip; 35*afbf1404SBin Meng u32 d03ip; 36*afbf1404SBin Meng u32 rsvd7[3]; 37*afbf1404SBin Meng u16 d31ir; 38*afbf1404SBin Meng u16 rsvd8[3]; 39*afbf1404SBin Meng u16 d27ir; 40*afbf1404SBin Meng u16 d26ir; 41*afbf1404SBin Meng u16 d25ir; 42*afbf1404SBin Meng u16 d24ir; 43*afbf1404SBin Meng u16 d23ir; 44*afbf1404SBin Meng u16 rsvd9[7]; 45*afbf1404SBin Meng u16 d02ir; 46*afbf1404SBin Meng u16 d03ir; 47*afbf1404SBin Meng }; 48adfe3b24SBin Meng 49adfe3b24SBin Meng #endif /* _X86_ARCH_TNC_H_ */ 50