1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2adfe3b24SBin Meng /* 3adfe3b24SBin Meng * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 4adfe3b24SBin Meng */ 5adfe3b24SBin Meng 6adfe3b24SBin Meng #ifndef _X86_ARCH_TNC_H_ 7adfe3b24SBin Meng #define _X86_ARCH_TNC_H_ 8adfe3b24SBin Meng 9e5ffa4bbSBin Meng /* IGD Function Disable Register */ 10e5ffa4bbSBin Meng #define IGD_FD 0xc4 11e5ffa4bbSBin Meng #define FUNC_DISABLE 0x00000001 121f124ebaSBin Meng 13afbf1404SBin Meng /* Memory BAR Enable */ 14afbf1404SBin Meng #define MEM_BAR_EN 0x00000001 15adfe3b24SBin Meng 16afbf1404SBin Meng /* LPC PCI Configuration Registers */ 17afbf1404SBin Meng #define LPC_RCBA 0xf0 18afbf1404SBin Meng 19afbf1404SBin Meng /* Root Complex Register Block */ 20afbf1404SBin Meng struct tnc_rcba { 21afbf1404SBin Meng u32 rctl; 22afbf1404SBin Meng u32 esd; 23afbf1404SBin Meng u32 rsvd1[2]; 24afbf1404SBin Meng u32 hdd; 25afbf1404SBin Meng u32 rsvd2; 26afbf1404SBin Meng u32 hdba; 27afbf1404SBin Meng u32 rsvd3[3129]; 28afbf1404SBin Meng u32 d31ip; 29afbf1404SBin Meng u32 rsvd4[3]; 30afbf1404SBin Meng u32 d27ip; 31afbf1404SBin Meng u32 rsvd5; 32afbf1404SBin Meng u32 d02ip; 33afbf1404SBin Meng u32 rsvd6; 34afbf1404SBin Meng u32 d26ip; 35afbf1404SBin Meng u32 d25ip; 36afbf1404SBin Meng u32 d24ip; 37afbf1404SBin Meng u32 d23ip; 38afbf1404SBin Meng u32 d03ip; 39afbf1404SBin Meng u32 rsvd7[3]; 40afbf1404SBin Meng u16 d31ir; 41afbf1404SBin Meng u16 rsvd8[3]; 42afbf1404SBin Meng u16 d27ir; 43afbf1404SBin Meng u16 d26ir; 44afbf1404SBin Meng u16 d25ir; 45afbf1404SBin Meng u16 d24ir; 46afbf1404SBin Meng u16 d23ir; 47afbf1404SBin Meng u16 rsvd9[7]; 48afbf1404SBin Meng u16 d02ir; 49afbf1404SBin Meng u16 d03ir; 50afbf1404SBin Meng }; 51adfe3b24SBin Meng 52adfe3b24SBin Meng #endif /* _X86_ARCH_TNC_H_ */ 53