1 /* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _QUARK_H_ 8 #define _QUARK_H_ 9 10 /* Message Bus Ports */ 11 #define MSG_PORT_MEM_ARBITER 0x00 12 #define MSG_PORT_HOST_BRIDGE 0x03 13 #define MSG_PORT_RMU 0x04 14 #define MSG_PORT_MEM_MGR 0x05 15 #define MSG_PORT_SOC_UNIT 0x31 16 17 /* Port 0x00: Memory Arbiter Message Port Registers */ 18 19 /* Enhanced Configuration Space */ 20 #define AEC_CTRL 0x00 21 22 /* Port 0x03: Host Bridge Message Port Registers */ 23 24 /* Host Memory I/O Boundary */ 25 #define HM_BOUND 0x08 26 27 /* Extended Configuration Space */ 28 #define HEC_REG 0x09 29 30 /* Port 0x04: Remote Management Unit Message Port Registers */ 31 32 /* ACPI PBLK Base Address Register */ 33 #define PBLK_BA 0x70 34 35 /* SPI DMA Base Address Register */ 36 #define SPI_DMA_BA 0x7a 37 38 /* Port 0x05: Memory Manager Message Port Registers */ 39 40 /* eSRAM Block Page Control */ 41 #define ESRAM_BLK_CTRL 0x82 42 #define ESRAM_BLOCK_MODE 0x10000000 43 44 /* DRAM */ 45 #define DRAM_BASE 0x00000000 46 #define DRAM_MAX_SIZE 0x80000000 47 48 /* eSRAM */ 49 #define ESRAM_SIZE 0x80000 50 51 /* Memory BAR Enable */ 52 #define MEM_BAR_EN 0x00000001 53 54 /* I/O BAR Enable */ 55 #define IO_BAR_EN 0x80000000 56 57 /* 64KiB of RMU binary in flash */ 58 #define RMU_BINARY_SIZE 0x10000 59 60 /* Legacy Bridge PCI Configuration Registers */ 61 #define LB_GBA 0x44 62 #define LB_PM1BLK 0x48 63 #define LB_GPE0BLK 0x4c 64 #define LB_ACTL 0x58 65 #define LB_PABCDRC 0x60 66 #define LB_PEFGHRC 0x64 67 #define LB_WDTBA 0x84 68 #define LB_BCE 0xd4 69 #define LB_BC 0xd8 70 #define LB_RCBA 0xf0 71 72 #endif /* _QUARK_H_ */ 73