1 /* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _QUARK_H_ 8 #define _QUARK_H_ 9 10 /* Message Bus Ports */ 11 #define MSG_PORT_MEM_ARBITER 0x00 12 #define MSG_PORT_HOST_BRIDGE 0x03 13 #define MSG_PORT_RMU 0x04 14 #define MSG_PORT_MEM_MGR 0x05 15 #define MSG_PORT_USB_AFE 0x14 16 #define MSG_PORT_PCIE_AFE 0x16 17 #define MSG_PORT_SOC_UNIT 0x31 18 19 /* Port 0x00: Memory Arbiter Message Port Registers */ 20 21 /* Enhanced Configuration Space */ 22 #define AEC_CTRL 0x00 23 24 /* Port 0x03: Host Bridge Message Port Registers */ 25 26 /* Host Miscellaneous Controls 2 */ 27 #define HMISC2 0x03 28 29 #define HMISC2_SEGE 0x00000002 30 #define HMISC2_SEGF 0x00000004 31 #define HMISC2_SEGAB 0x00000010 32 33 /* Host Memory I/O Boundary */ 34 #define HM_BOUND 0x08 35 #define HM_BOUND_LOCK 0x00000001 36 37 /* Extended Configuration Space */ 38 #define HEC_REG 0x09 39 40 /* MTRR Registers */ 41 #define MTRR_CAP 0x40 42 #define MTRR_DEF_TYPE 0x41 43 44 #define MTRR_FIX_64K_00000 0x42 45 #define MTRR_FIX_64K_40000 0x43 46 #define MTRR_FIX_16K_80000 0x44 47 #define MTRR_FIX_16K_90000 0x45 48 #define MTRR_FIX_16K_A0000 0x46 49 #define MTRR_FIX_16K_B0000 0x47 50 #define MTRR_FIX_4K_C0000 0x48 51 #define MTRR_FIX_4K_C4000 0x49 52 #define MTRR_FIX_4K_C8000 0x4a 53 #define MTRR_FIX_4K_CC000 0x4b 54 #define MTRR_FIX_4K_D0000 0x4c 55 #define MTRR_FIX_4K_D4000 0x4d 56 #define MTRR_FIX_4K_D8000 0x4e 57 #define MTRR_FIX_4K_DC000 0x4f 58 #define MTRR_FIX_4K_E0000 0x50 59 #define MTRR_FIX_4K_E4000 0x51 60 #define MTRR_FIX_4K_E8000 0x52 61 #define MTRR_FIX_4K_EC000 0x53 62 #define MTRR_FIX_4K_F0000 0x54 63 #define MTRR_FIX_4K_F4000 0x55 64 #define MTRR_FIX_4K_F8000 0x56 65 #define MTRR_FIX_4K_FC000 0x57 66 67 #define MTRR_SMRR_PHYBASE 0x58 68 #define MTRR_SMRR_PHYMASK 0x59 69 70 #define MTRR_VAR_PHYBASE(n) (0x5a + 2 * (n)) 71 #define MTRR_VAR_PHYMASK(n) (0x5b + 2 * (n)) 72 73 #ifndef __ASSEMBLY__ 74 75 /* variable range MTRR usage */ 76 enum { 77 MTRR_VAR_ROM, 78 MTRR_VAR_ESRAM, 79 MTRR_VAR_RAM 80 }; 81 82 #endif /* __ASSEMBLY__ */ 83 84 /* Port 0x04: Remote Management Unit Message Port Registers */ 85 86 /* ACPI PBLK Base Address Register */ 87 #define PBLK_BA 0x70 88 89 /* Control Register */ 90 #define RMU_CTRL 0x71 91 92 /* SPI DMA Base Address Register */ 93 #define SPI_DMA_BA 0x7a 94 95 /* Thermal Sensor Register */ 96 #define TS_MODE 0xb0 97 #define TS_TEMP 0xb1 98 #define TS_TRIP 0xb2 99 100 /* Port 0x05: Memory Manager Message Port Registers */ 101 102 /* eSRAM Block Page Control */ 103 #define ESRAM_BLK_CTRL 0x82 104 #define ESRAM_BLOCK_MODE 0x10000000 105 106 /* Port 0x14: USB2 AFE Unit Port Registers */ 107 108 #define USB2_GLOBAL_PORT 0x4001 109 #define USB2_PLL1 0x7f02 110 #define USB2_PLL2 0x7f03 111 #define USB2_COMPBG 0x7f04 112 113 /* Port 0x16: PCIe AFE Unit Port Registers */ 114 115 #define PCIE_RXPICTRL0_L0 0x2080 116 #define PCIE_RXPICTRL0_L1 0x2180 117 118 /* Port 0x31: SoC Unit Port Registers */ 119 120 /* Thermal Sensor Config */ 121 #define TS_CFG1 0x31 122 #define TS_CFG2 0x32 123 #define TS_CFG3 0x33 124 #define TS_CFG4 0x34 125 126 /* PCIe Controller Config */ 127 #define PCIE_CFG 0x36 128 #define PCIE_CTLR_PRI_RST 0x00010000 129 #define PCIE_PHY_SB_RST 0x00020000 130 #define PCIE_CTLR_SB_RST 0x00040000 131 #define PCIE_PHY_LANE_RST 0x00090000 132 #define PCIE_CTLR_MAIN_RST 0x00100000 133 134 /* DRAM */ 135 #define DRAM_BASE 0x00000000 136 #define DRAM_MAX_SIZE 0x80000000 137 138 /* eSRAM */ 139 #define ESRAM_SIZE 0x80000 140 141 /* Memory BAR Enable */ 142 #define MEM_BAR_EN 0x00000001 143 144 /* I/O BAR Enable */ 145 #define IO_BAR_EN 0x80000000 146 147 /* 64KiB of RMU binary in flash */ 148 #define RMU_BINARY_SIZE 0x10000 149 150 /* PCIe Root Port Configuration Registers */ 151 152 #define PCIE_RP_CCFG 0xd0 153 #define CCFG_UPRS (1 << 14) 154 #define CCFG_UNRS (1 << 15) 155 #define CCFG_UNSD (1 << 23) 156 #define CCFG_UPSD (1 << 24) 157 158 #define PCIE_RP_MPC2 0xd4 159 #define MPC2_IPF (1 << 11) 160 161 #define PCIE_RP_MBC 0xf4 162 #define MBC_SBIC (3 << 16) 163 164 /* Legacy Bridge PCI Configuration Registers */ 165 #define LB_GBA 0x44 166 #define LB_PM1BLK 0x48 167 #define LB_GPE0BLK 0x4c 168 #define LB_ACTL 0x58 169 #define LB_PABCDRC 0x60 170 #define LB_PEFGHRC 0x64 171 #define LB_WDTBA 0x84 172 #define LB_BCE 0xd4 173 #define LB_BC 0xd8 174 #define LB_RCBA 0xf0 175 176 /* USB EHCI memory-mapped registers */ 177 #define EHCI_INSNREG01 0x94 178 179 /* USB device memory-mapped registers */ 180 #define USBD_INT_MASK 0x410 181 #define USBD_EP_INT_STS 0x414 182 #define USBD_EP_INT_MASK 0x418 183 184 #ifndef __ASSEMBLY__ 185 186 /* Root Complex Register Block */ 187 struct quark_rcba { 188 u32 rctl; 189 u32 esd; 190 u32 rsvd1[3150]; 191 u16 rmu_ir; 192 u16 d23_ir; 193 u16 core_ir; 194 u16 d20d21_ir; 195 }; 196 197 #include <asm/io.h> 198 #include <asm/pci.h> 199 200 /** 201 * qrk_pci_read_config_dword() - Read a configuration value 202 * 203 * @dev: PCI device address: bus, device and function 204 * @offset: Dword offset within the device's configuration space 205 * @valuep: Place to put the returned value 206 * 207 * Note: This routine is inlined to provide better performance on Quark 208 */ 209 static inline void qrk_pci_read_config_dword(pci_dev_t dev, int offset, 210 u32 *valuep) 211 { 212 outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR); 213 *valuep = inl(PCI_REG_DATA); 214 } 215 216 /** 217 * qrk_pci_write_config_dword() - Write a PCI configuration value 218 * 219 * @dev: PCI device address: bus, device and function 220 * @offset: Dword offset within the device's configuration space 221 * @value: Value to write 222 * 223 * Note: This routine is inlined to provide better performance on Quark 224 */ 225 static inline void qrk_pci_write_config_dword(pci_dev_t dev, int offset, 226 u32 value) 227 { 228 outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR); 229 outl(value, PCI_REG_DATA); 230 } 231 232 /** 233 * board_assert_perst() - Assert the PERST# pin 234 * 235 * The CPU interface to the PERST# signal on Quark is platform dependent. 236 * Board-specific codes need supply this routine to assert PCIe slot reset. 237 * 238 * The tricky part in this routine is that any APIs that may trigger PCI 239 * enumeration process are strictly forbidden, as any access to PCIe root 240 * port's configuration registers will cause system hang while it is held 241 * in reset. 242 */ 243 void board_assert_perst(void); 244 245 /** 246 * board_deassert_perst() - De-assert the PERST# pin 247 * 248 * The CPU interface to the PERST# signal on Quark is platform dependent. 249 * Board-specific codes need supply this routine to de-assert PCIe slot reset. 250 * 251 * The tricky part in this routine is that any APIs that may trigger PCI 252 * enumeration process are strictly forbidden, as any access to PCIe root 253 * port's configuration registers will cause system hang while it is held 254 * in reset. 255 */ 256 void board_deassert_perst(void); 257 258 #endif /* __ASSEMBLY__ */ 259 260 #endif /* _QUARK_H_ */ 261