1 /* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _QUARK_H_ 8 #define _QUARK_H_ 9 10 /* Message Bus Ports */ 11 #define MSG_PORT_MEM_ARBITER 0x00 12 #define MSG_PORT_HOST_BRIDGE 0x03 13 #define MSG_PORT_RMU 0x04 14 #define MSG_PORT_MEM_MGR 0x05 15 #define MSG_PORT_USB_AFE 0x14 16 #define MSG_PORT_PCIE_AFE 0x16 17 #define MSG_PORT_SOC_UNIT 0x31 18 19 /* Port 0x00: Memory Arbiter Message Port Registers */ 20 21 /* Enhanced Configuration Space */ 22 #define AEC_CTRL 0x00 23 24 /* Port 0x03: Host Bridge Message Port Registers */ 25 26 /* Host Miscellaneous Controls 2 */ 27 #define HMISC2 0x03 28 29 #define HMISC2_SEGE 0x00000002 30 #define HMISC2_SEGF 0x00000004 31 #define HMISC2_SEGAB 0x00000010 32 33 /* Host Memory I/O Boundary */ 34 #define HM_BOUND 0x08 35 36 /* Extended Configuration Space */ 37 #define HEC_REG 0x09 38 39 /* Port 0x04: Remote Management Unit Message Port Registers */ 40 41 /* ACPI PBLK Base Address Register */ 42 #define PBLK_BA 0x70 43 44 /* SPI DMA Base Address Register */ 45 #define SPI_DMA_BA 0x7a 46 47 /* Port 0x05: Memory Manager Message Port Registers */ 48 49 /* eSRAM Block Page Control */ 50 #define ESRAM_BLK_CTRL 0x82 51 #define ESRAM_BLOCK_MODE 0x10000000 52 53 /* Port 0x14: USB2 AFE Unit Port Registers */ 54 55 #define USB2_GLOBAL_PORT 0x4001 56 #define USB2_PLL1 0x7f02 57 #define USB2_PLL2 0x7f03 58 #define USB2_COMPBG 0x7f04 59 60 /* Port 0x16: PCIe AFE Unit Port Registers */ 61 62 #define PCIE_RXPICTRL0_L0 0x2080 63 #define PCIE_RXPICTRL0_L1 0x2180 64 65 /* Port 0x31: SoC Unit Port Registers */ 66 67 /* PCIe Controller Config */ 68 #define PCIE_CFG 0x36 69 #define PCIE_CTLR_PRI_RST 0x00010000 70 #define PCIE_PHY_SB_RST 0x00020000 71 #define PCIE_CTLR_SB_RST 0x00040000 72 #define PCIE_PHY_LANE_RST 0x00090000 73 #define PCIE_CTLR_MAIN_RST 0x00100000 74 75 /* DRAM */ 76 #define DRAM_BASE 0x00000000 77 #define DRAM_MAX_SIZE 0x80000000 78 79 /* eSRAM */ 80 #define ESRAM_SIZE 0x80000 81 82 /* Memory BAR Enable */ 83 #define MEM_BAR_EN 0x00000001 84 85 /* I/O BAR Enable */ 86 #define IO_BAR_EN 0x80000000 87 88 /* 64KiB of RMU binary in flash */ 89 #define RMU_BINARY_SIZE 0x10000 90 91 /* Legacy Bridge PCI Configuration Registers */ 92 #define LB_GBA 0x44 93 #define LB_PM1BLK 0x48 94 #define LB_GPE0BLK 0x4c 95 #define LB_ACTL 0x58 96 #define LB_PABCDRC 0x60 97 #define LB_PEFGHRC 0x64 98 #define LB_WDTBA 0x84 99 #define LB_BCE 0xd4 100 #define LB_BC 0xd8 101 #define LB_RCBA 0xf0 102 103 #ifndef __ASSEMBLY__ 104 105 /* Root Complex Register Block */ 106 struct quark_rcba { 107 u32 rctl; 108 u32 esd; 109 u32 rsvd1[3150]; 110 u16 rmu_ir; 111 u16 d23_ir; 112 u16 core_ir; 113 u16 d20d21_ir; 114 }; 115 116 #include <asm/io.h> 117 #include <asm/pci.h> 118 119 /** 120 * qrk_pci_read_config_dword() - Read a configuration value 121 * 122 * @dev: PCI device address: bus, device and function 123 * @offset: Dword offset within the device's configuration space 124 * @valuep: Place to put the returned value 125 * 126 * Note: This routine is inlined to provide better performance on Quark 127 */ 128 static inline void qrk_pci_read_config_dword(pci_dev_t dev, int offset, 129 u32 *valuep) 130 { 131 outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR); 132 *valuep = inl(PCI_REG_DATA); 133 } 134 135 /** 136 * qrk_pci_write_config_dword() - Write a PCI configuration value 137 * 138 * @dev: PCI device address: bus, device and function 139 * @offset: Dword offset within the device's configuration space 140 * @value: Value to write 141 * 142 * Note: This routine is inlined to provide better performance on Quark 143 */ 144 static inline void qrk_pci_write_config_dword(pci_dev_t dev, int offset, 145 u32 value) 146 { 147 outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR); 148 outl(value, PCI_REG_DATA); 149 } 150 151 /** 152 * board_assert_perst() - Assert the PERST# pin 153 * 154 * The CPU interface to the PERST# signal on Quark is platform dependent. 155 * Board-specific codes need supply this routine to assert PCIe slot reset. 156 * 157 * The tricky part in this routine is that any APIs that may trigger PCI 158 * enumeration process are strictly forbidden, as any access to PCIe root 159 * port's configuration registers will cause system hang while it is held 160 * in reset. 161 */ 162 void board_assert_perst(void); 163 164 /** 165 * board_deassert_perst() - De-assert the PERST# pin 166 * 167 * The CPU interface to the PERST# signal on Quark is platform dependent. 168 * Board-specific codes need supply this routine to de-assert PCIe slot reset. 169 * 170 * The tricky part in this routine is that any APIs that may trigger PCI 171 * enumeration process are strictly forbidden, as any access to PCIe root 172 * port's configuration registers will cause system hang while it is held 173 * in reset. 174 */ 175 void board_deassert_perst(void); 176 177 #endif /* __ASSEMBLY__ */ 178 179 #endif /* _QUARK_H_ */ 180