1 /* 2 * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _QUARK_IOMAP_H_ 8 #define _QUARK_IOMAP_H_ 9 10 /* Memory Mapped IO bases */ 11 12 /* ESRAM */ 13 #define ESRAM_BASE_ADDRESS CONFIG_ESRAM_BASE 14 #define ESRAM_BASE_SIZE ESRAM_SIZE 15 16 /* PCI Configuration Space */ 17 #define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE 18 #define MCFG_BASE_SIZE 0x10000000 19 20 /* High Performance Event Timer */ 21 #define HPET_BASE_ADDRESS 0xfed00000 22 #define HPET_BASE_SIZE 0x400 23 24 /* Root Complex Base Address */ 25 #define RCBA_BASE_ADDRESS CONFIG_RCBA_BASE 26 #define RCBA_BASE_SIZE 0x4000 27 28 /* IO Port bases */ 29 #define ACPI_PM1_BASE_ADDRESS CONFIG_ACPI_PM1_BASE 30 #define ACPI_PM1_BASE_SIZE 0x10 31 32 #define ACPI_PBLK_BASE_ADDRESS CONFIG_ACPI_PBLK_BASE 33 #define ACPI_PBLK_BASE_SIZE 0x10 34 35 #define SPI_DMA_BASE_ADDRESS CONFIG_SPI_DMA_BASE 36 #define SPI_DMA_BASE_SIZE 0x10 37 38 #define GPIO_BASE_ADDRESS CONFIG_GPIO_BASE 39 #define GPIO_BASE_SIZE 0x80 40 41 #define ACPI_GPE0_BASE_ADDRESS CONFIG_ACPI_GPE0_BASE 42 #define ACPI_GPE0_BASE_SIZE 0x40 43 44 #define WDT_BASE_ADDRESS CONFIG_WDT_BASE 45 #define WDT_BASE_SIZE 0x40 46 47 #endif /* _QUARK_IOMAP_H_ */ 48