1 /* 2 * Copyright (c) 2014 Google, Inc 3 * 4 * From Coreboot file of the same name 5 * 6 * Copyright (C) 2007-2008 coresystems GmbH 7 * Copyright (C) 2011 Google Inc. 8 * 9 * SPDX-License-Identifier: GPL-2.0 10 */ 11 12 #ifndef _ACH_ASM_SANDYBRIDGE_H 13 #define _ACH_ASM_SANDYBRIDGE_H 14 15 /* Chipset types */ 16 #define SANDYBRIDGE_MOBILE 0 17 #define SANDYBRIDGE_DESKTOP 1 18 #define SANDYBRIDGE_SERVER 2 19 20 /* Device ID for SandyBridge and IvyBridge */ 21 #define BASE_REV_SNB 0x00 22 #define BASE_REV_IVB 0x50 23 #define BASE_REV_MASK 0x50 24 25 /* SandyBridge CPU stepping */ 26 #define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */ 27 #define SNB_STEP_D1 (BASE_REV_SNB + 6) 28 #define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */ 29 30 /* IvyBridge CPU stepping */ 31 #define IVB_STEP_A0 (BASE_REV_IVB + 0) 32 #define IVB_STEP_B0 (BASE_REV_IVB + 2) 33 #define IVB_STEP_C0 (BASE_REV_IVB + 4) 34 #define IVB_STEP_K0 (BASE_REV_IVB + 5) 35 #define IVB_STEP_D0 (BASE_REV_IVB + 6) 36 37 /* Intel Enhanced Debug region must be 4MB */ 38 #define IED_SIZE 0x400000 39 40 /* Northbridge BARs */ 41 #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ 42 #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ 43 #define DEFAULT_RCBABASE 0xfed1c000 44 /* 4 KB per PCIe device */ 45 #define DEFAULT_PCIEXBAR CONFIG_PCIE_ECAM_BASE 46 47 /* Device 0:0.0 PCI configuration space (Host Bridge) */ 48 #define EPBAR 0x40 49 #define MCHBAR 0x48 50 #define PCIEXBAR 0x60 51 #define DMIBAR 0x68 52 #define X60BAR 0x60 53 54 #define GGC 0x50 /* GMCH Graphics Control */ 55 56 #define DEVEN 0x54 /* Device Enable */ 57 #define DEVEN_PEG60 (1 << 13) 58 #define DEVEN_IGD (1 << 4) 59 #define DEVEN_PEG10 (1 << 3) 60 #define DEVEN_PEG11 (1 << 2) 61 #define DEVEN_PEG12 (1 << 1) 62 #define DEVEN_HOST (1 << 0) 63 64 #define PAM0 0x80 65 #define PAM1 0x81 66 #define PAM2 0x82 67 #define PAM3 0x83 68 #define PAM4 0x84 69 #define PAM5 0x85 70 #define PAM6 0x86 71 72 #define LAC 0x87 /* Legacy Access Control */ 73 #define SMRAM 0x88 /* System Management RAM Control */ 74 #define D_OPEN (1 << 6) 75 #define D_CLS (1 << 5) 76 #define D_LCK (1 << 4) 77 #define G_SMRAME (1 << 3) 78 #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) 79 80 #define TOM 0xa0 81 #define TOUUD 0xa8 /* Top of Upper Usable DRAM */ 82 #define TSEG 0xb8 /* TSEG base */ 83 #define TOLUD 0xbc /* Top of Low Used Memory */ 84 85 #define SKPAD 0xdc /* Scratchpad Data */ 86 87 /* Device 0:1.0 PCI configuration space (PCI Express) */ 88 #define BCTRL1 0x3e /* 16bit */ 89 90 /* Device 0:2.0 PCI configuration space (Graphics Device) */ 91 92 #define MSAC 0x62 /* Multi Size Aperture Control */ 93 #define SWSCI 0xe8 /* SWSCI enable */ 94 #define ASLS 0xfc /* OpRegion Base */ 95 96 /* 97 * MCHBAR 98 */ 99 #define SSKPD 0x5d14 /* 16bit (scratchpad) */ 100 #define BIOS_RESET_CPL 0x5da8 /* 8bit */ 101 102 /* 103 * DMIBAR 104 */ 105 106 #define DMIBAR_REG(x) (DEFAULT_DMIBAR + x) 107 108 /** 109 * bridge_silicon_revision() - Get the Northbridge revision 110 * 111 * @dev: Northbridge device 112 * @return revision ID (bits 3:0) and bridge ID (bits 7:4) 113 */ 114 int bridge_silicon_revision(struct udevice *dev); 115 116 #endif 117