1 /* 2 * Copyright (c) 2011, Google Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef ASM_ARCH_PEI_DATA_H 8 #define ASM_ARCH_PEI_DATA_H 9 10 struct pch_usb3_controller_settings { 11 /* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */ 12 uint16_t mode; 13 /* 4 bit mask, 1: switchable, 0: not switchable */ 14 uint16_t hs_port_switch_mask; 15 /* 0: No xHCI preOS driver, 1: xHCI preOS driver */ 16 uint16_t preboot_support; 17 /* 0: Disable, 1: Enable */ 18 uint16_t xhci_streams; 19 }; 20 21 typedef asmlinkage void (*tx_byte_func)(unsigned char byte); 22 23 #define PEI_VERSION 6 24 25 struct __packed pei_data { 26 uint32_t pei_version; 27 uint32_t mchbar; 28 uint32_t dmibar; 29 uint32_t epbar; 30 uint32_t pciexbar; 31 uint16_t smbusbar; 32 uint32_t wdbbar; 33 uint32_t wdbsize; 34 uint32_t hpet_address; 35 uint32_t rcba; 36 uint32_t pmbase; 37 uint32_t gpiobase; 38 uint32_t thermalbase; 39 uint32_t system_type; /* 0 Mobile, 1 Desktop/Server */ 40 uint32_t tseg_size; 41 uint8_t spd_addresses[4]; 42 uint8_t ts_addresses[4]; 43 int boot_mode; 44 int ec_present; 45 int gbe_enable; 46 /* 47 * 0 = leave channel enabled 48 * 1 = disable dimm 0 on channel 49 * 2 = disable dimm 1 on channel 50 * 3 = disable dimm 0+1 on channel 51 */ 52 int dimm_channel0_disabled; 53 int dimm_channel1_disabled; 54 /* Seed values saved in CMOS */ 55 uint32_t scrambler_seed; 56 uint32_t scrambler_seed_s3; 57 /* Data read from flash and passed into MRC */ 58 unsigned char *mrc_input; 59 unsigned int mrc_input_len; 60 /* Data from MRC that should be saved to flash */ 61 unsigned char *mrc_output; 62 unsigned int mrc_output_len; 63 /* 64 * Max frequency DDR3 could be ran at. Could be one of four values: 65 * 800, 1067, 1333, 1600 66 */ 67 uint32_t max_ddr3_freq; 68 /* 69 * USB Port Configuration: 70 * [0] = enable 71 * [1] = overcurrent pin 72 * [2] = length 73 * 74 * Ports 0-7 can be mapped to OC0-OC3 75 * Ports 8-13 can be mapped to OC4-OC7 76 * 77 * Port Length 78 * MOBILE: 79 * < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude) 80 * < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude) 81 * DESKTOP: 82 * < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude) 83 * < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude) 84 * < 0x150 = Setting 3 (back panel, 13-15in, higest tx amplitude) 85 */ 86 uint16_t usb_port_config[16][3]; 87 /* See the usb3 struct above for details */ 88 struct pch_usb3_controller_settings usb3; 89 /* 90 * SPD data array for onboard RAM. Specify address 0xf0, 91 * 0xf1, 0xf2, 0xf3 to index one of the 4 slots in 92 * spd_address for a given "DIMM". 93 */ 94 uint8_t spd_data[4][256]; 95 tx_byte_func tx_byte; 96 int ddr3lv_support; 97 /* 98 * pcie_init needs to be set to 1 to have the system agent initialise 99 * PCIe. Note: This should only be required if your system has Gen3 100 * devices and it will increase your boot time by at least 100ms. 101 */ 102 int pcie_init; 103 /* 104 * N mode functionality. Leave this setting at 0. 105 * 0 Auto 106 * 1 1N 107 * 2 2N 108 */ 109 int nmode; 110 /* 111 * DDR refresh rate config. JEDEC Standard No.21-C Annex K allows 112 * for DIMM SPD data to specify whether double-rate is required for 113 * extended operating temperature range. 114 * 0 Enable double rate based upon temperature thresholds 115 * 1 Normal rate 116 * 2 Always enable double rate 117 */ 118 int ddr_refresh_rate_config; 119 }; 120 121 #endif 122