1 /* 2 * Copyright (c) 2011, Google Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef ASM_ARCH_PEI_DATA_H 8 #define ASM_ARCH_PEI_DATA_H 9 10 #include <linux/linkage.h> 11 12 struct pch_usb3_controller_settings { 13 /* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */ 14 uint16_t mode; 15 /* 4 bit mask, 1: switchable, 0: not switchable */ 16 uint16_t hs_port_switch_mask; 17 /* 0: No xHCI preOS driver, 1: xHCI preOS driver */ 18 uint16_t preboot_support; 19 /* 0: Disable, 1: Enable */ 20 uint16_t xhci_streams; 21 }; 22 23 typedef asmlinkage void (*tx_byte_func)(unsigned char byte); 24 25 #define PEI_VERSION 6 26 27 struct __packed pei_data { 28 uint32_t pei_version; 29 uint32_t mchbar; 30 uint32_t dmibar; 31 uint32_t epbar; 32 uint32_t pciexbar; 33 uint16_t smbusbar; 34 uint32_t wdbbar; 35 uint32_t wdbsize; 36 uint32_t hpet_address; 37 uint32_t rcba; 38 uint32_t pmbase; 39 uint32_t gpiobase; 40 uint32_t thermalbase; 41 uint32_t system_type; /* 0 Mobile, 1 Desktop/Server */ 42 uint32_t tseg_size; 43 uint8_t spd_addresses[4]; 44 uint8_t ts_addresses[4]; 45 int boot_mode; 46 int ec_present; 47 int gbe_enable; 48 /* 49 * 0 = leave channel enabled 50 * 1 = disable dimm 0 on channel 51 * 2 = disable dimm 1 on channel 52 * 3 = disable dimm 0+1 on channel 53 */ 54 int dimm_channel0_disabled; 55 int dimm_channel1_disabled; 56 /* Seed values saved in CMOS */ 57 uint32_t scrambler_seed; 58 uint32_t scrambler_seed_s3; 59 /* Data read from flash and passed into MRC */ 60 unsigned char *mrc_input; 61 unsigned int mrc_input_len; 62 /* Data from MRC that should be saved to flash */ 63 unsigned char *mrc_output; 64 unsigned int mrc_output_len; 65 /* 66 * Max frequency DDR3 could be ran at. Could be one of four values: 67 * 800, 1067, 1333, 1600 68 */ 69 uint32_t max_ddr3_freq; 70 /* 71 * USB Port Configuration: 72 * [0] = enable 73 * [1] = overcurrent pin 74 * [2] = length 75 * 76 * Ports 0-7 can be mapped to OC0-OC3 77 * Ports 8-13 can be mapped to OC4-OC7 78 * 79 * Port Length 80 * MOBILE: 81 * < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude) 82 * < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude) 83 * DESKTOP: 84 * < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude) 85 * < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude) 86 * < 0x150 = Setting 3 (back panel, 13-15in, higest tx amplitude) 87 */ 88 uint16_t usb_port_config[16][3]; 89 /* See the usb3 struct above for details */ 90 struct pch_usb3_controller_settings usb3; 91 /* 92 * SPD data array for onboard RAM. Specify address 0xf0, 93 * 0xf1, 0xf2, 0xf3 to index one of the 4 slots in 94 * spd_address for a given "DIMM". 95 */ 96 uint8_t spd_data[4][256]; 97 tx_byte_func tx_byte; 98 int ddr3lv_support; 99 /* 100 * pcie_init needs to be set to 1 to have the system agent initialise 101 * PCIe. Note: This should only be required if your system has Gen3 102 * devices and it will increase your boot time by at least 100ms. 103 */ 104 int pcie_init; 105 /* 106 * N mode functionality. Leave this setting at 0. 107 * 0 Auto 108 * 1 1N 109 * 2 2N 110 */ 111 int nmode; 112 /* 113 * DDR refresh rate config. JEDEC Standard No.21-C Annex K allows 114 * for DIMM SPD data to specify whether double-rate is required for 115 * extended operating temperature range. 116 * 0 Enable double rate based upon temperature thresholds 117 * 1 Normal rate 118 * 2 Always enable double rate 119 */ 120 int ddr_refresh_rate_config; 121 }; 122 123 #endif 124