1 /* 2 * Copyright (c) 2014 Google, Inc 3 * 4 * From Coreboot src/southbridge/intel/bd82x6x/pch.h 5 * 6 * Copyright (C) 2008-2009 coresystems GmbH 7 * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. 8 * 9 * SPDX-License-Identifier: GPL-2.0 10 */ 11 12 #ifndef _ASM_ARCH_PCH_H 13 #define _ASM_ARCH_PCH_H 14 15 #include <pci.h> 16 17 #define DEFAULT_GPIOBASE 0x0480 18 #define DEFAULT_PMBASE 0x0500 19 20 #define SMBUS_IO_BASE 0x0400 21 22 #define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0) 23 #define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0) 24 #define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0) 25 #define PCH_ME_DEV PCI_BDF(0, 0x16, 0) 26 #define PCH_PCIE_DEV_SLOT 28 27 28 #define PCH_DEV PCI_BDF(0, 0, 0) 29 #define PCH_VIDEO_DEV PCI_BDF(0, 2, 0) 30 31 /* PCI Configuration Space (D31:F0): LPC */ 32 #define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0) 33 34 #define GEN_PMCON_1 0xa0 35 #define GEN_PMCON_2 0xa2 36 #define GEN_PMCON_3 0xa4 37 #define ETR3 0xac 38 #define ETR3_CWORWRE (1 << 18) 39 #define ETR3_CF9GR (1 << 20) 40 41 #define PMBASE 0x40 42 #define ACPI_CNTL 0x44 43 #define BIOS_CNTL 0xDC 44 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ 45 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ 46 #define GPIO_ROUT 0xb8 47 48 #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ 49 #define LPC_EN 0x82 /* LPC IF Enables Register */ 50 #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ 51 #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ 52 #define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ 53 #define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ 54 #define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ 55 #define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ 56 #define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ 57 #define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ 58 #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ 59 #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ 60 #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ 61 #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ 62 #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ 63 #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ 64 #define LPC_GENX_DEC(x) (0x84 + 4 * (x)) 65 66 /* PCI Configuration Space (D31:F3): SMBus */ 67 #define PCH_SMBUS_DEV PCI_BDF(0, 0x1f, 3) 68 #define SMB_BASE 0x20 69 #define HOSTC 0x40 70 #define SMB_RCV_SLVA 0x09 71 72 /* HOSTC bits */ 73 #define I2C_EN (1 << 2) 74 #define SMB_SMI_EN (1 << 1) 75 #define HST_EN (1 << 0) 76 77 /* SMBus I/O bits. */ 78 #define SMBHSTSTAT 0x0 79 #define SMBHSTCTL 0x2 80 #define SMBHSTCMD 0x3 81 #define SMBXMITADD 0x4 82 #define SMBHSTDAT0 0x5 83 #define SMBHSTDAT1 0x6 84 #define SMBBLKDAT 0x7 85 #define SMBTRNSADD 0x9 86 #define SMBSLVDATA 0xa 87 #define SMLINK_PIN_CTL 0xe 88 #define SMBUS_PIN_CTL 0xf 89 90 #define SMBUS_TIMEOUT (10 * 1000 * 100) 91 92 93 /* Root Complex Register Block */ 94 #define DEFAULT_RCBA 0xfed1c000 95 #define RCB_REG(reg) (DEFAULT_RCBA + (reg)) 96 97 #define PCH_RCBA_BASE 0xf0 98 99 #define VCH 0x0000 /* 32bit */ 100 #define VCAP1 0x0004 /* 32bit */ 101 #define VCAP2 0x0008 /* 32bit */ 102 #define PVC 0x000c /* 16bit */ 103 #define PVS 0x000e /* 16bit */ 104 105 #define V0CAP 0x0010 /* 32bit */ 106 #define V0CTL 0x0014 /* 32bit */ 107 #define V0STS 0x001a /* 16bit */ 108 109 #define V1CAP 0x001c /* 32bit */ 110 #define V1CTL 0x0020 /* 32bit */ 111 #define V1STS 0x0026 /* 16bit */ 112 113 #define RCTCL 0x0100 /* 32bit */ 114 #define ESD 0x0104 /* 32bit */ 115 #define ULD 0x0110 /* 32bit */ 116 #define ULBA 0x0118 /* 64bit */ 117 118 #define RP1D 0x0120 /* 32bit */ 119 #define RP1BA 0x0128 /* 64bit */ 120 #define RP2D 0x0130 /* 32bit */ 121 #define RP2BA 0x0138 /* 64bit */ 122 #define RP3D 0x0140 /* 32bit */ 123 #define RP3BA 0x0148 /* 64bit */ 124 #define RP4D 0x0150 /* 32bit */ 125 #define RP4BA 0x0158 /* 64bit */ 126 #define HDD 0x0160 /* 32bit */ 127 #define HDBA 0x0168 /* 64bit */ 128 #define RP5D 0x0170 /* 32bit */ 129 #define RP5BA 0x0178 /* 64bit */ 130 #define RP6D 0x0180 /* 32bit */ 131 #define RP6BA 0x0188 /* 64bit */ 132 133 #define RPC 0x0400 /* 32bit */ 134 #define RPFN 0x0404 /* 32bit */ 135 136 #define TRSR 0x1e00 /* 8bit */ 137 #define TRCR 0x1e10 /* 64bit */ 138 #define TWDR 0x1e18 /* 64bit */ 139 140 #define IOTR0 0x1e80 /* 64bit */ 141 #define IOTR1 0x1e88 /* 64bit */ 142 #define IOTR2 0x1e90 /* 64bit */ 143 #define IOTR3 0x1e98 /* 64bit */ 144 145 #define TCTL 0x3000 /* 8bit */ 146 147 #define NOINT 0 148 #define INTA 1 149 #define INTB 2 150 #define INTC 3 151 #define INTD 4 152 153 #define DIR_IDR 12 /* Interrupt D Pin Offset */ 154 #define DIR_ICR 8 /* Interrupt C Pin Offset */ 155 #define DIR_IBR 4 /* Interrupt B Pin Offset */ 156 #define DIR_IAR 0 /* Interrupt A Pin Offset */ 157 158 #define PIRQA 0 159 #define PIRQB 1 160 #define PIRQC 2 161 #define PIRQD 3 162 #define PIRQE 4 163 #define PIRQF 5 164 #define PIRQG 6 165 #define PIRQH 7 166 167 /* IO Buffer Programming */ 168 #define IOBPIRI 0x2330 169 #define IOBPD 0x2334 170 #define IOBPS 0x2338 171 #define IOBPS_RW_BX ((1 << 9)|(1 << 10)) 172 #define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) 173 #define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) 174 175 #define D31IP 0x3100 /* 32bit */ 176 #define D31IP_TTIP 24 /* Thermal Throttle Pin */ 177 #define D31IP_SIP2 20 /* SATA Pin 2 */ 178 #define D31IP_SMIP 12 /* SMBUS Pin */ 179 #define D31IP_SIP 8 /* SATA Pin */ 180 #define D30IP 0x3104 /* 32bit */ 181 #define D30IP_PIP 0 /* PCI Bridge Pin */ 182 #define D29IP 0x3108 /* 32bit */ 183 #define D29IP_E1P 0 /* EHCI #1 Pin */ 184 #define D28IP 0x310c /* 32bit */ 185 #define D28IP_P8IP 28 /* PCI Express Port 8 */ 186 #define D28IP_P7IP 24 /* PCI Express Port 7 */ 187 #define D28IP_P6IP 20 /* PCI Express Port 6 */ 188 #define D28IP_P5IP 16 /* PCI Express Port 5 */ 189 #define D28IP_P4IP 12 /* PCI Express Port 4 */ 190 #define D28IP_P3IP 8 /* PCI Express Port 3 */ 191 #define D28IP_P2IP 4 /* PCI Express Port 2 */ 192 #define D28IP_P1IP 0 /* PCI Express Port 1 */ 193 #define D27IP 0x3110 /* 32bit */ 194 #define D27IP_ZIP 0 /* HD Audio Pin */ 195 #define D26IP 0x3114 /* 32bit */ 196 #define D26IP_E2P 0 /* EHCI #2 Pin */ 197 #define D25IP 0x3118 /* 32bit */ 198 #define D25IP_LIP 0 /* GbE LAN Pin */ 199 #define D22IP 0x3124 /* 32bit */ 200 #define D22IP_KTIP 12 /* KT Pin */ 201 #define D22IP_IDERIP 8 /* IDE-R Pin */ 202 #define D22IP_MEI2IP 4 /* MEI #2 Pin */ 203 #define D22IP_MEI1IP 0 /* MEI #1 Pin */ 204 #define D20IP 0x3128 /* 32bit */ 205 #define D20IP_XHCIIP 0 206 #define D31IR 0x3140 /* 16bit */ 207 #define D30IR 0x3142 /* 16bit */ 208 #define D29IR 0x3144 /* 16bit */ 209 #define D28IR 0x3146 /* 16bit */ 210 #define D27IR 0x3148 /* 16bit */ 211 #define D26IR 0x314c /* 16bit */ 212 #define D25IR 0x3150 /* 16bit */ 213 #define D22IR 0x315c /* 16bit */ 214 #define D20IR 0x3160 /* 16bit */ 215 #define OIC 0x31fe /* 16bit */ 216 217 #define SPI_FREQ_SWSEQ 0x3893 218 #define SPI_DESC_COMP0 0x38b0 219 #define SPI_FREQ_WR_ERA 0x38b4 220 #define SOFT_RESET_CTRL 0x38f4 221 #define SOFT_RESET_DATA 0x38f8 222 223 #define DIR_ROUTE(a, b, c, d) \ 224 (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ 225 ((b) << DIR_IBR) | ((a) << DIR_IAR)) 226 227 #define RC 0x3400 /* 32bit */ 228 #define HPTC 0x3404 /* 32bit */ 229 #define GCS 0x3410 /* 32bit */ 230 #define BUC 0x3414 /* 32bit */ 231 #define PCH_DISABLE_GBE (1 << 5) 232 #define FD 0x3418 /* 32bit */ 233 #define DISPBDF 0x3424 /* 16bit */ 234 #define FD2 0x3428 /* 32bit */ 235 #define CG 0x341c /* 32bit */ 236 237 /* Function Disable 1 RCBA 0x3418 */ 238 #define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)) 239 #define PCH_DISABLE_P2P (1 << 1) 240 #define PCH_DISABLE_SATA1 (1 << 2) 241 #define PCH_DISABLE_SMBUS (1 << 3) 242 #define PCH_DISABLE_HD_AUDIO (1 << 4) 243 #define PCH_DISABLE_EHCI2 (1 << 13) 244 #define PCH_DISABLE_LPC (1 << 14) 245 #define PCH_DISABLE_EHCI1 (1 << 15) 246 #define PCH_DISABLE_PCIE(x) (1 << (16 + x)) 247 #define PCH_DISABLE_THERMAL (1 << 24) 248 #define PCH_DISABLE_SATA2 (1 << 25) 249 #define PCH_DISABLE_XHCI (1 << 27) 250 251 /* Function Disable 2 RCBA 0x3428 */ 252 #define PCH_DISABLE_KT (1 << 4) 253 #define PCH_DISABLE_IDER (1 << 3) 254 #define PCH_DISABLE_MEI2 (1 << 2) 255 #define PCH_DISABLE_MEI1 (1 << 1) 256 #define PCH_ENABLE_DBDF (1 << 0) 257 258 /* ICH7 GPIOBASE */ 259 #define GPIO_USE_SEL 0x00 260 #define GP_IO_SEL 0x04 261 #define GP_LVL 0x0c 262 #define GPO_BLINK 0x18 263 #define GPI_INV 0x2c 264 #define GPIO_USE_SEL2 0x30 265 #define GP_IO_SEL2 0x34 266 #define GP_LVL2 0x38 267 #define GPIO_USE_SEL3 0x40 268 #define GP_IO_SEL3 0x44 269 #define GP_LVL3 0x48 270 #define GP_RST_SEL1 0x60 271 #define GP_RST_SEL2 0x64 272 #define GP_RST_SEL3 0x68 273 274 /* ICH7 PMBASE */ 275 #define PM1_STS 0x00 276 #define WAK_STS (1 << 15) 277 #define PCIEXPWAK_STS (1 << 14) 278 #define PRBTNOR_STS (1 << 11) 279 #define RTC_STS (1 << 10) 280 #define PWRBTN_STS (1 << 8) 281 #define GBL_STS (1 << 5) 282 #define BM_STS (1 << 4) 283 #define TMROF_STS (1 << 0) 284 #define PM1_EN 0x02 285 #define PCIEXPWAK_DIS (1 << 14) 286 #define RTC_EN (1 << 10) 287 #define PWRBTN_EN (1 << 8) 288 #define GBL_EN (1 << 5) 289 #define TMROF_EN (1 << 0) 290 #define PM1_CNT 0x04 291 #define SLP_EN (1 << 13) 292 #define SLP_TYP (7 << 10) 293 #define SLP_TYP_S0 0 294 #define SLP_TYP_S1 1 295 #define SLP_TYP_S3 5 296 #define SLP_TYP_S4 6 297 #define SLP_TYP_S5 7 298 #define GBL_RLS (1 << 2) 299 #define BM_RLD (1 << 1) 300 #define SCI_EN (1 << 0) 301 #define PM1_TMR 0x08 302 #define PROC_CNT 0x10 303 #define LV2 0x14 304 #define LV3 0x15 305 #define LV4 0x16 306 #define PM2_CNT 0x50 /* mobile only */ 307 #define GPE0_STS 0x20 308 #define PME_B0_STS (1 << 13) 309 #define PME_STS (1 << 11) 310 #define BATLOW_STS (1 << 10) 311 #define PCI_EXP_STS (1 << 9) 312 #define RI_STS (1 << 8) 313 #define SMB_WAK_STS (1 << 7) 314 #define TCOSCI_STS (1 << 6) 315 #define SWGPE_STS (1 << 2) 316 #define HOT_PLUG_STS (1 << 1) 317 #define GPE0_EN 0x28 318 #define PME_B0_EN (1 << 13) 319 #define PME_EN (1 << 11) 320 #define TCOSCI_EN (1 << 6) 321 #define SMI_EN 0x30 322 #define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */ 323 #define LEGACY_USB2_EN (1 << 17) /* Legacy USB2 SMI logic */ 324 #define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */ 325 #define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */ 326 #define MCSMI_EN (1 << 11) /* Trap microcontroller range access */ 327 #define BIOS_RLS (1 << 7) /* asserts SCI on bit set */ 328 #define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */ 329 #define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */ 330 #define SLP_SMI_EN (1 << 4) /* Write SLP_EN in PM1_CNT asserts SMI# */ 331 #define LEGACY_USB_EN (1 << 3) /* Legacy USB circuit SMI logic */ 332 #define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */ 333 #define EOS (1 << 1) /* End of SMI (deassert SMI#) */ 334 #define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */ 335 #define SMI_STS 0x34 336 #define ALT_GP_SMI_EN 0x38 337 #define ALT_GP_SMI_STS 0x3a 338 #define GPE_CNTL 0x42 339 #define DEVACT_STS 0x44 340 #define SS_CNT 0x50 341 #define C3_RES 0x54 342 #define TCO1_STS 0x64 343 #define DMISCI_STS (1 << 9) 344 #define TCO2_STS 0x66 345 346 /** 347 * lpc_early_init() - set up LPC serial ports and other early things 348 * 349 * @blob: Device tree blob 350 * @node: Offset of LPC node 351 * @dev: PCH PCI device containing the LPC 352 * @return 0 if OK, -ve on error 353 */ 354 int lpc_early_init(const void *blob, int node, pci_dev_t dev); 355 356 #endif 357