1 /* 2 * Copyright (c) 2014 Google, Inc 3 * 4 * From Coreboot src/southbridge/intel/bd82x6x/pch.h 5 * 6 * Copyright (C) 2008-2009 coresystems GmbH 7 * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. 8 * 9 * SPDX-License-Identifier: GPL-2.0 10 */ 11 12 #ifndef _ASM_ARCH_PCH_H 13 #define _ASM_ARCH_PCH_H 14 15 #include <pci.h> 16 17 /* PCH types */ 18 #define PCH_TYPE_CPT 0x1c /* CougarPoint */ 19 #define PCH_TYPE_PPT 0x1e /* IvyBridge */ 20 21 /* PCH stepping values for LPC device */ 22 #define PCH_STEP_A0 0 23 #define PCH_STEP_A1 1 24 #define PCH_STEP_B0 2 25 #define PCH_STEP_B1 3 26 #define PCH_STEP_B2 4 27 #define PCH_STEP_B3 5 28 #define DEFAULT_GPIOBASE 0x0480 29 #define DEFAULT_PMBASE 0x0500 30 31 #define SMBUS_IO_BASE 0x0400 32 33 #define MAINBOARD_POWER_OFF 0 34 #define MAINBOARD_POWER_ON 1 35 #define MAINBOARD_POWER_KEEP 2 36 37 /* PCI Configuration Space (D30:F0): PCI2PCI */ 38 #define PSTS 0x06 39 #define SMLT 0x1b 40 #define SECSTS 0x1e 41 #define INTR 0x3c 42 #define BCTRL 0x3e 43 #define SBR (1 << 6) 44 #define SEE (1 << 1) 45 #define PERE (1 << 0) 46 47 #define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0) 48 #define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0) 49 #define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0) 50 #define PCH_ME_DEV PCI_BDF(0, 0x16, 0) 51 #define PCH_PCIE_DEV_SLOT 28 52 53 #define PCH_DEV PCI_BDF(0, 0, 0) 54 #define PCH_VIDEO_DEV PCI_BDF(0, 2, 0) 55 56 /* PCI Configuration Space (D31:F0): LPC */ 57 #define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0) 58 #define SERIRQ_CNTL 0x64 59 60 #define GEN_PMCON_1 0xa0 61 #define GEN_PMCON_2 0xa2 62 #define GEN_PMCON_3 0xa4 63 #define ETR3 0xac 64 #define ETR3_CWORWRE (1 << 18) 65 #define ETR3_CF9GR (1 << 20) 66 67 /* GEN_PMCON_3 bits */ 68 #define RTC_BATTERY_DEAD (1 << 2) 69 #define RTC_POWER_FAILED (1 << 1) 70 #define SLEEP_AFTER_POWER_FAIL (1 << 0) 71 72 #define BIOS_CNTL 0xDC 73 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ 74 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ 75 #define GPIO_ROUT 0xb8 76 77 #define PIRQA_ROUT 0x60 78 #define PIRQB_ROUT 0x61 79 #define PIRQC_ROUT 0x62 80 #define PIRQD_ROUT 0x63 81 #define PIRQE_ROUT 0x68 82 #define PIRQF_ROUT 0x69 83 #define PIRQG_ROUT 0x6A 84 #define PIRQH_ROUT 0x6B 85 86 #define GEN_PMCON_1 0xa0 87 #define GEN_PMCON_2 0xa2 88 #define GEN_PMCON_3 0xa4 89 #define ETR3 0xac 90 #define ETR3_CWORWRE (1 << 18) 91 #define ETR3_CF9GR (1 << 20) 92 93 #define PMBASE 0x40 94 #define ACPI_CNTL 0x44 95 #define BIOS_CNTL 0xDC 96 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ 97 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ 98 #define GPIO_ROUT 0xb8 99 100 /* PCI Configuration Space (D31:F1): IDE */ 101 #define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1) 102 #define PCH_SATA_DEV PCI_BDF(0, 0x1f, 2) 103 #define PCH_SATA2_DEV PCI_BDF(0, 0x1f, 5) 104 105 #define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ 106 #define IDE_SSDE1 (1 << 3) 107 #define IDE_SSDE0 (1 << 2) 108 #define IDE_PSDE1 (1 << 1) 109 #define IDE_PSDE0 (1 << 0) 110 111 #define IDE_SDMA_TIM 0x4a 112 113 #define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ 114 #define SIG_MODE_SEC_NORMAL (0 << 18) 115 #define SIG_MODE_SEC_TRISTATE (1 << 18) 116 #define SIG_MODE_SEC_DRIVELOW (2 << 18) 117 #define SIG_MODE_PRI_NORMAL (0 << 16) 118 #define SIG_MODE_PRI_TRISTATE (1 << 16) 119 #define SIG_MODE_PRI_DRIVELOW (2 << 16) 120 #define FAST_SCB1 (1 << 15) 121 #define FAST_SCB0 (1 << 14) 122 #define FAST_PCB1 (1 << 13) 123 #define FAST_PCB0 (1 << 12) 124 #define SCB1 (1 << 3) 125 #define SCB0 (1 << 2) 126 #define PCB1 (1 << 1) 127 #define PCB0 (1 << 0) 128 129 #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ 130 #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ 131 #define SATA_SP 0xd0 /* Scratchpad */ 132 133 /* SATA IOBP Registers */ 134 #define SATA_IOBP_SP0G3IR 0xea000151 135 #define SATA_IOBP_SP1G3IR 0xea000051 136 137 /* PCI Configuration Space (D31:F3): SMBus */ 138 #define PCH_SMBUS_DEV PCI_BDF(0, 0x1f, 3) 139 #define SMB_BASE 0x20 140 #define HOSTC 0x40 141 #define SMB_RCV_SLVA 0x09 142 143 /* HOSTC bits */ 144 #define I2C_EN (1 << 2) 145 #define SMB_SMI_EN (1 << 1) 146 #define HST_EN (1 << 0) 147 148 /* SMBus I/O bits. */ 149 #define SMBHSTSTAT 0x0 150 #define SMBHSTCTL 0x2 151 #define SMBHSTCMD 0x3 152 #define SMBXMITADD 0x4 153 #define SMBHSTDAT0 0x5 154 #define SMBHSTDAT1 0x6 155 #define SMBBLKDAT 0x7 156 #define SMBTRNSADD 0x9 157 #define SMBSLVDATA 0xa 158 #define SMLINK_PIN_CTL 0xe 159 #define SMBUS_PIN_CTL 0xf 160 161 #define SMBUS_TIMEOUT (10 * 1000 * 100) 162 163 #define VCH 0x0000 /* 32bit */ 164 #define VCAP1 0x0004 /* 32bit */ 165 #define VCAP2 0x0008 /* 32bit */ 166 #define PVC 0x000c /* 16bit */ 167 #define PVS 0x000e /* 16bit */ 168 169 #define V0CAP 0x0010 /* 32bit */ 170 #define V0CTL 0x0014 /* 32bit */ 171 #define V0STS 0x001a /* 16bit */ 172 173 #define V1CAP 0x001c /* 32bit */ 174 #define V1CTL 0x0020 /* 32bit */ 175 #define V1STS 0x0026 /* 16bit */ 176 177 #define RCTCL 0x0100 /* 32bit */ 178 #define ESD 0x0104 /* 32bit */ 179 #define ULD 0x0110 /* 32bit */ 180 #define ULBA 0x0118 /* 64bit */ 181 182 #define RP1D 0x0120 /* 32bit */ 183 #define RP1BA 0x0128 /* 64bit */ 184 #define RP2D 0x0130 /* 32bit */ 185 #define RP2BA 0x0138 /* 64bit */ 186 #define RP3D 0x0140 /* 32bit */ 187 #define RP3BA 0x0148 /* 64bit */ 188 #define RP4D 0x0150 /* 32bit */ 189 #define RP4BA 0x0158 /* 64bit */ 190 #define HDD 0x0160 /* 32bit */ 191 #define HDBA 0x0168 /* 64bit */ 192 #define RP5D 0x0170 /* 32bit */ 193 #define RP5BA 0x0178 /* 64bit */ 194 #define RP6D 0x0180 /* 32bit */ 195 #define RP6BA 0x0188 /* 64bit */ 196 197 #define RPC 0x0400 /* 32bit */ 198 #define RPFN 0x0404 /* 32bit */ 199 200 #define TRSR 0x1e00 /* 8bit */ 201 #define TRCR 0x1e10 /* 64bit */ 202 #define TWDR 0x1e18 /* 64bit */ 203 204 #define IOTR0 0x1e80 /* 64bit */ 205 #define IOTR1 0x1e88 /* 64bit */ 206 #define IOTR2 0x1e90 /* 64bit */ 207 #define IOTR3 0x1e98 /* 64bit */ 208 209 #define TCTL 0x3000 /* 8bit */ 210 211 #define NOINT 0 212 #define INTA 1 213 #define INTB 2 214 #define INTC 3 215 #define INTD 4 216 217 #define DIR_IDR 12 /* Interrupt D Pin Offset */ 218 #define DIR_ICR 8 /* Interrupt C Pin Offset */ 219 #define DIR_IBR 4 /* Interrupt B Pin Offset */ 220 #define DIR_IAR 0 /* Interrupt A Pin Offset */ 221 222 #define PIRQA 0 223 #define PIRQB 1 224 #define PIRQC 2 225 #define PIRQD 3 226 #define PIRQE 4 227 #define PIRQF 5 228 #define PIRQG 6 229 #define PIRQH 7 230 231 /* IO Buffer Programming */ 232 #define IOBPIRI 0x2330 233 #define IOBPD 0x2334 234 #define IOBPS 0x2338 235 #define IOBPS_RW_BX ((1 << 9)|(1 << 10)) 236 #define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) 237 #define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) 238 239 #define D31IP 0x3100 /* 32bit */ 240 #define D31IP_TTIP 24 /* Thermal Throttle Pin */ 241 #define D31IP_SIP2 20 /* SATA Pin 2 */ 242 #define D31IP_SMIP 12 /* SMBUS Pin */ 243 #define D31IP_SIP 8 /* SATA Pin */ 244 #define D30IP 0x3104 /* 32bit */ 245 #define D30IP_PIP 0 /* PCI Bridge Pin */ 246 #define D29IP 0x3108 /* 32bit */ 247 #define D29IP_E1P 0 /* EHCI #1 Pin */ 248 #define D28IP 0x310c /* 32bit */ 249 #define D28IP_P8IP 28 /* PCI Express Port 8 */ 250 #define D28IP_P7IP 24 /* PCI Express Port 7 */ 251 #define D28IP_P6IP 20 /* PCI Express Port 6 */ 252 #define D28IP_P5IP 16 /* PCI Express Port 5 */ 253 #define D28IP_P4IP 12 /* PCI Express Port 4 */ 254 #define D28IP_P3IP 8 /* PCI Express Port 3 */ 255 #define D28IP_P2IP 4 /* PCI Express Port 2 */ 256 #define D28IP_P1IP 0 /* PCI Express Port 1 */ 257 #define D27IP 0x3110 /* 32bit */ 258 #define D27IP_ZIP 0 /* HD Audio Pin */ 259 #define D26IP 0x3114 /* 32bit */ 260 #define D26IP_E2P 0 /* EHCI #2 Pin */ 261 #define D25IP 0x3118 /* 32bit */ 262 #define D25IP_LIP 0 /* GbE LAN Pin */ 263 #define D22IP 0x3124 /* 32bit */ 264 #define D22IP_KTIP 12 /* KT Pin */ 265 #define D22IP_IDERIP 8 /* IDE-R Pin */ 266 #define D22IP_MEI2IP 4 /* MEI #2 Pin */ 267 #define D22IP_MEI1IP 0 /* MEI #1 Pin */ 268 #define D20IP 0x3128 /* 32bit */ 269 #define D20IP_XHCIIP 0 270 #define D31IR 0x3140 /* 16bit */ 271 #define D30IR 0x3142 /* 16bit */ 272 #define D29IR 0x3144 /* 16bit */ 273 #define D28IR 0x3146 /* 16bit */ 274 #define D27IR 0x3148 /* 16bit */ 275 #define D26IR 0x314c /* 16bit */ 276 #define D25IR 0x3150 /* 16bit */ 277 #define D22IR 0x315c /* 16bit */ 278 #define D20IR 0x3160 /* 16bit */ 279 #define OIC 0x31fe /* 16bit */ 280 281 #define SPI_FREQ_SWSEQ 0x3893 282 #define SPI_DESC_COMP0 0x38b0 283 #define SPI_FREQ_WR_ERA 0x38b4 284 285 #define DIR_ROUTE(a, b, c, d) \ 286 (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ 287 ((b) << DIR_IBR) | ((a) << DIR_IAR)) 288 289 #define HPTC 0x3404 /* 32bit */ 290 #define BUC 0x3414 /* 32bit */ 291 #define PCH_DISABLE_GBE (1 << 5) 292 #define FD 0x3418 /* 32bit */ 293 #define DISPBDF 0x3424 /* 16bit */ 294 #define FD2 0x3428 /* 32bit */ 295 #define CG 0x341c /* 32bit */ 296 297 /* Function Disable 1 RCBA 0x3418 */ 298 #define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)) 299 #define PCH_DISABLE_P2P (1 << 1) 300 #define PCH_DISABLE_SATA1 (1 << 2) 301 #define PCH_DISABLE_SMBUS (1 << 3) 302 #define PCH_DISABLE_HD_AUDIO (1 << 4) 303 #define PCH_DISABLE_EHCI2 (1 << 13) 304 #define PCH_DISABLE_LPC (1 << 14) 305 #define PCH_DISABLE_EHCI1 (1 << 15) 306 #define PCH_DISABLE_PCIE(x) (1 << (16 + x)) 307 #define PCH_DISABLE_THERMAL (1 << 24) 308 #define PCH_DISABLE_SATA2 (1 << 25) 309 #define PCH_DISABLE_XHCI (1 << 27) 310 311 /* Function Disable 2 RCBA 0x3428 */ 312 #define PCH_DISABLE_KT (1 << 4) 313 #define PCH_DISABLE_IDER (1 << 3) 314 #define PCH_DISABLE_MEI2 (1 << 2) 315 #define PCH_DISABLE_MEI1 (1 << 1) 316 #define PCH_ENABLE_DBDF (1 << 0) 317 318 /* ICH7 GPIOBASE */ 319 #define GPIO_USE_SEL 0x00 320 #define GP_IO_SEL 0x04 321 #define GP_LVL 0x0c 322 #define GPO_BLINK 0x18 323 #define GPI_INV 0x2c 324 #define GPIO_USE_SEL2 0x30 325 #define GP_IO_SEL2 0x34 326 #define GP_LVL2 0x38 327 #define GPIO_USE_SEL3 0x40 328 #define GP_IO_SEL3 0x44 329 #define GP_LVL3 0x48 330 #define GP_RST_SEL1 0x60 331 #define GP_RST_SEL2 0x64 332 #define GP_RST_SEL3 0x68 333 334 /* ICH7 PMBASE */ 335 #define PM1_STS 0x00 336 #define WAK_STS (1 << 15) 337 #define PCIEXPWAK_STS (1 << 14) 338 #define PRBTNOR_STS (1 << 11) 339 #define RTC_STS (1 << 10) 340 #define PWRBTN_STS (1 << 8) 341 #define GBL_STS (1 << 5) 342 #define BM_STS (1 << 4) 343 #define TMROF_STS (1 << 0) 344 #define PM1_EN 0x02 345 #define PCIEXPWAK_DIS (1 << 14) 346 #define RTC_EN (1 << 10) 347 #define PWRBTN_EN (1 << 8) 348 #define GBL_EN (1 << 5) 349 #define TMROF_EN (1 << 0) 350 #define PM1_CNT 0x04 351 #define SLP_EN (1 << 13) 352 #define SLP_TYP (7 << 10) 353 #define SLP_TYP_S0 0 354 #define SLP_TYP_S1 1 355 #define SLP_TYP_S3 5 356 #define SLP_TYP_S4 6 357 #define SLP_TYP_S5 7 358 #define GBL_RLS (1 << 2) 359 #define BM_RLD (1 << 1) 360 #define SCI_EN (1 << 0) 361 #define PM1_TMR 0x08 362 #define PROC_CNT 0x10 363 #define LV2 0x14 364 #define LV3 0x15 365 #define LV4 0x16 366 #define PM2_CNT 0x50 /* mobile only */ 367 #define GPE0_STS 0x20 368 #define PME_B0_STS (1 << 13) 369 #define PME_STS (1 << 11) 370 #define BATLOW_STS (1 << 10) 371 #define PCI_EXP_STS (1 << 9) 372 #define RI_STS (1 << 8) 373 #define SMB_WAK_STS (1 << 7) 374 #define TCOSCI_STS (1 << 6) 375 #define SWGPE_STS (1 << 2) 376 #define HOT_PLUG_STS (1 << 1) 377 #define GPE0_EN 0x28 378 #define PME_B0_EN (1 << 13) 379 #define PME_EN (1 << 11) 380 #define TCOSCI_EN (1 << 6) 381 #define SMI_EN 0x30 382 #define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */ 383 #define LEGACY_USB2_EN (1 << 17) /* Legacy USB2 SMI logic */ 384 #define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */ 385 #define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */ 386 #define MCSMI_EN (1 << 11) /* Trap microcontroller range access */ 387 #define BIOS_RLS (1 << 7) /* asserts SCI on bit set */ 388 #define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */ 389 #define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */ 390 #define SLP_SMI_EN (1 << 4) /* Write SLP_EN in PM1_CNT asserts SMI# */ 391 #define LEGACY_USB_EN (1 << 3) /* Legacy USB circuit SMI logic */ 392 #define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */ 393 #define EOS (1 << 1) /* End of SMI (deassert SMI#) */ 394 #define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */ 395 #define SMI_STS 0x34 396 #define ALT_GP_SMI_EN 0x38 397 #define ALT_GP_SMI_STS 0x3a 398 #define GPE_CNTL 0x42 399 #define DEVACT_STS 0x44 400 #define SS_CNT 0x50 401 #define C3_RES 0x54 402 #define TCO1_STS 0x64 403 #define DMISCI_STS (1 << 9) 404 #define TCO2_STS 0x66 405 406 /** 407 * pch_silicon_revision() - Read silicon device ID from the PCH 408 * 409 * @dev: PCH device 410 * @return silicon device ID 411 */ 412 int pch_silicon_type(struct udevice *dev); 413 414 /** 415 * pch_pch_iobp_update() - Update a pch register 416 * 417 * @dev: PCH device 418 * @address: Address to update 419 * @andvalue: Value to AND with existing value 420 * @orvalue: Value to OR with existing value 421 */ 422 void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue, 423 u32 orvalue); 424 425 #endif 426