1 /* 2 * Copyright (c) 2014 Google, Inc 3 * 4 * From Coreboot src/southbridge/intel/bd82x6x/pch.h 5 * 6 * Copyright (C) 2008-2009 coresystems GmbH 7 * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. 8 * 9 * SPDX-License-Identifier: GPL-2.0 10 */ 11 12 #ifndef _ASM_ARCH_PCH_H 13 #define _ASM_ARCH_PCH_H 14 15 #include <pci.h> 16 17 /* PCH types */ 18 #define PCH_TYPE_CPT 0x1c /* CougarPoint */ 19 #define PCH_TYPE_PPT 0x1e /* IvyBridge */ 20 21 /* PCH stepping values for LPC device */ 22 #define PCH_STEP_A0 0 23 #define PCH_STEP_A1 1 24 #define PCH_STEP_B0 2 25 #define PCH_STEP_B1 3 26 #define PCH_STEP_B2 4 27 #define PCH_STEP_B3 5 28 #define DEFAULT_GPIOBASE 0x0480 29 #define DEFAULT_PMBASE 0x0500 30 31 #define SMBUS_IO_BASE 0x0400 32 33 #define MAINBOARD_POWER_OFF 0 34 #define MAINBOARD_POWER_ON 1 35 #define MAINBOARD_POWER_KEEP 2 36 37 /* PCI Configuration Space (D30:F0): PCI2PCI */ 38 #define PSTS 0x06 39 #define SMLT 0x1b 40 #define SECSTS 0x1e 41 #define INTR 0x3c 42 #define BCTRL 0x3e 43 #define SBR (1 << 6) 44 #define SEE (1 << 1) 45 #define PERE (1 << 0) 46 47 #define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0) 48 #define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0) 49 #define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0) 50 #define PCH_ME_DEV PCI_BDF(0, 0x16, 0) 51 #define PCH_PCIE_DEV_SLOT 28 52 53 #define PCH_DEV PCI_BDF(0, 0, 0) 54 #define PCH_VIDEO_DEV PCI_BDF(0, 2, 0) 55 56 /* PCI Configuration Space (D31:F0): LPC */ 57 #define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0) 58 #define SERIRQ_CNTL 0x64 59 60 #define GEN_PMCON_1 0xa0 61 #define GEN_PMCON_2 0xa2 62 #define GEN_PMCON_3 0xa4 63 #define ETR3 0xac 64 #define ETR3_CWORWRE (1 << 18) 65 #define ETR3_CF9GR (1 << 20) 66 67 /* GEN_PMCON_3 bits */ 68 #define RTC_BATTERY_DEAD (1 << 2) 69 #define RTC_POWER_FAILED (1 << 1) 70 #define SLEEP_AFTER_POWER_FAIL (1 << 0) 71 72 #define PMBASE 0x40 73 #define ACPI_CNTL 0x44 74 #define BIOS_CNTL 0xDC 75 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ 76 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ 77 #define GPIO_ROUT 0xb8 78 79 #define PIRQA_ROUT 0x60 80 #define PIRQB_ROUT 0x61 81 #define PIRQC_ROUT 0x62 82 #define PIRQD_ROUT 0x63 83 #define PIRQE_ROUT 0x68 84 #define PIRQF_ROUT 0x69 85 #define PIRQG_ROUT 0x6A 86 #define PIRQH_ROUT 0x6B 87 88 #define GEN_PMCON_1 0xa0 89 #define GEN_PMCON_2 0xa2 90 #define GEN_PMCON_3 0xa4 91 #define ETR3 0xac 92 #define ETR3_CWORWRE (1 << 18) 93 #define ETR3_CF9GR (1 << 20) 94 95 #define PMBASE 0x40 96 #define ACPI_CNTL 0x44 97 #define BIOS_CNTL 0xDC 98 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ 99 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ 100 #define GPIO_ROUT 0xb8 101 102 #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ 103 #define COMB_DEC_RANGE (1 << 4) /* 0x2f8-0x2ff (COM2) */ 104 #define COMA_DEC_RANGE (0 << 0) /* 0x3f8-0x3ff (COM1) */ 105 #define LPC_EN 0x82 /* LPC IF Enables Register */ 106 #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ 107 #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ 108 #define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ 109 #define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ 110 #define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ 111 #define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ 112 #define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ 113 #define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ 114 #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ 115 #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ 116 #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ 117 #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ 118 #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ 119 #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ 120 #define LPC_GENX_DEC(x) (0x84 + 4 * (x)) 121 #define GEN_DEC_RANGE_256B 0xfc0000 /* 256 Bytes */ 122 #define GEN_DEC_RANGE_128B 0x7c0000 /* 128 Bytes */ 123 #define GEN_DEC_RANGE_64B 0x3c0000 /* 64 Bytes */ 124 #define GEN_DEC_RANGE_32B 0x1c0000 /* 32 Bytes */ 125 #define GEN_DEC_RANGE_16B 0x0c0000 /* 16 Bytes */ 126 #define GEN_DEC_RANGE_8B 0x040000 /* 8 Bytes */ 127 #define GEN_DEC_RANGE_4B 0x000000 /* 4 Bytes */ 128 #define GEN_DEC_RANGE_EN (1 << 0) /* Range Enable */ 129 130 /* PCI Configuration Space (D31:F1): IDE */ 131 #define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1) 132 #define PCH_SATA_DEV PCI_BDF(0, 0x1f, 2) 133 #define PCH_SATA2_DEV PCI_BDF(0, 0x1f, 5) 134 135 #define INTR_LN 0x3c 136 #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ 137 #define IDE_DECODE_ENABLE (1 << 15) 138 #define IDE_SITRE (1 << 14) 139 #define IDE_ISP_5_CLOCKS (0 << 12) 140 #define IDE_ISP_4_CLOCKS (1 << 12) 141 #define IDE_ISP_3_CLOCKS (2 << 12) 142 #define IDE_RCT_4_CLOCKS (0 << 8) 143 #define IDE_RCT_3_CLOCKS (1 << 8) 144 #define IDE_RCT_2_CLOCKS (2 << 8) 145 #define IDE_RCT_1_CLOCKS (3 << 8) 146 #define IDE_DTE1 (1 << 7) 147 #define IDE_PPE1 (1 << 6) 148 #define IDE_IE1 (1 << 5) 149 #define IDE_TIME1 (1 << 4) 150 #define IDE_DTE0 (1 << 3) 151 #define IDE_PPE0 (1 << 2) 152 #define IDE_IE0 (1 << 1) 153 #define IDE_TIME0 (1 << 0) 154 #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ 155 156 #define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ 157 #define IDE_SSDE1 (1 << 3) 158 #define IDE_SSDE0 (1 << 2) 159 #define IDE_PSDE1 (1 << 1) 160 #define IDE_PSDE0 (1 << 0) 161 162 #define IDE_SDMA_TIM 0x4a 163 164 #define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ 165 #define SIG_MODE_SEC_NORMAL (0 << 18) 166 #define SIG_MODE_SEC_TRISTATE (1 << 18) 167 #define SIG_MODE_SEC_DRIVELOW (2 << 18) 168 #define SIG_MODE_PRI_NORMAL (0 << 16) 169 #define SIG_MODE_PRI_TRISTATE (1 << 16) 170 #define SIG_MODE_PRI_DRIVELOW (2 << 16) 171 #define FAST_SCB1 (1 << 15) 172 #define FAST_SCB0 (1 << 14) 173 #define FAST_PCB1 (1 << 13) 174 #define FAST_PCB0 (1 << 12) 175 #define SCB1 (1 << 3) 176 #define SCB0 (1 << 2) 177 #define PCB1 (1 << 1) 178 #define PCB0 (1 << 0) 179 180 #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ 181 #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ 182 #define SATA_SP 0xd0 /* Scratchpad */ 183 184 /* SATA IOBP Registers */ 185 #define SATA_IOBP_SP0G3IR 0xea000151 186 #define SATA_IOBP_SP1G3IR 0xea000051 187 188 /* PCI Configuration Space (D31:F3): SMBus */ 189 #define PCH_SMBUS_DEV PCI_BDF(0, 0x1f, 3) 190 #define SMB_BASE 0x20 191 #define HOSTC 0x40 192 #define SMB_RCV_SLVA 0x09 193 194 /* HOSTC bits */ 195 #define I2C_EN (1 << 2) 196 #define SMB_SMI_EN (1 << 1) 197 #define HST_EN (1 << 0) 198 199 /* SMBus I/O bits. */ 200 #define SMBHSTSTAT 0x0 201 #define SMBHSTCTL 0x2 202 #define SMBHSTCMD 0x3 203 #define SMBXMITADD 0x4 204 #define SMBHSTDAT0 0x5 205 #define SMBHSTDAT1 0x6 206 #define SMBBLKDAT 0x7 207 #define SMBTRNSADD 0x9 208 #define SMBSLVDATA 0xa 209 #define SMLINK_PIN_CTL 0xe 210 #define SMBUS_PIN_CTL 0xf 211 212 #define SMBUS_TIMEOUT (10 * 1000 * 100) 213 214 215 /* Root Complex Register Block */ 216 #define DEFAULT_RCBA 0xfed1c000 217 #define RCB_REG(reg) (DEFAULT_RCBA + (reg)) 218 219 #define PCH_RCBA_BASE 0xf0 220 221 #define VCH 0x0000 /* 32bit */ 222 #define VCAP1 0x0004 /* 32bit */ 223 #define VCAP2 0x0008 /* 32bit */ 224 #define PVC 0x000c /* 16bit */ 225 #define PVS 0x000e /* 16bit */ 226 227 #define V0CAP 0x0010 /* 32bit */ 228 #define V0CTL 0x0014 /* 32bit */ 229 #define V0STS 0x001a /* 16bit */ 230 231 #define V1CAP 0x001c /* 32bit */ 232 #define V1CTL 0x0020 /* 32bit */ 233 #define V1STS 0x0026 /* 16bit */ 234 235 #define RCTCL 0x0100 /* 32bit */ 236 #define ESD 0x0104 /* 32bit */ 237 #define ULD 0x0110 /* 32bit */ 238 #define ULBA 0x0118 /* 64bit */ 239 240 #define RP1D 0x0120 /* 32bit */ 241 #define RP1BA 0x0128 /* 64bit */ 242 #define RP2D 0x0130 /* 32bit */ 243 #define RP2BA 0x0138 /* 64bit */ 244 #define RP3D 0x0140 /* 32bit */ 245 #define RP3BA 0x0148 /* 64bit */ 246 #define RP4D 0x0150 /* 32bit */ 247 #define RP4BA 0x0158 /* 64bit */ 248 #define HDD 0x0160 /* 32bit */ 249 #define HDBA 0x0168 /* 64bit */ 250 #define RP5D 0x0170 /* 32bit */ 251 #define RP5BA 0x0178 /* 64bit */ 252 #define RP6D 0x0180 /* 32bit */ 253 #define RP6BA 0x0188 /* 64bit */ 254 255 #define RPC 0x0400 /* 32bit */ 256 #define RPFN 0x0404 /* 32bit */ 257 258 #define TRSR 0x1e00 /* 8bit */ 259 #define TRCR 0x1e10 /* 64bit */ 260 #define TWDR 0x1e18 /* 64bit */ 261 262 #define IOTR0 0x1e80 /* 64bit */ 263 #define IOTR1 0x1e88 /* 64bit */ 264 #define IOTR2 0x1e90 /* 64bit */ 265 #define IOTR3 0x1e98 /* 64bit */ 266 267 #define TCTL 0x3000 /* 8bit */ 268 269 #define NOINT 0 270 #define INTA 1 271 #define INTB 2 272 #define INTC 3 273 #define INTD 4 274 275 #define DIR_IDR 12 /* Interrupt D Pin Offset */ 276 #define DIR_ICR 8 /* Interrupt C Pin Offset */ 277 #define DIR_IBR 4 /* Interrupt B Pin Offset */ 278 #define DIR_IAR 0 /* Interrupt A Pin Offset */ 279 280 #define PIRQA 0 281 #define PIRQB 1 282 #define PIRQC 2 283 #define PIRQD 3 284 #define PIRQE 4 285 #define PIRQF 5 286 #define PIRQG 6 287 #define PIRQH 7 288 289 /* IO Buffer Programming */ 290 #define IOBPIRI 0x2330 291 #define IOBPD 0x2334 292 #define IOBPS 0x2338 293 #define IOBPS_RW_BX ((1 << 9)|(1 << 10)) 294 #define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) 295 #define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) 296 297 #define D31IP 0x3100 /* 32bit */ 298 #define D31IP_TTIP 24 /* Thermal Throttle Pin */ 299 #define D31IP_SIP2 20 /* SATA Pin 2 */ 300 #define D31IP_SMIP 12 /* SMBUS Pin */ 301 #define D31IP_SIP 8 /* SATA Pin */ 302 #define D30IP 0x3104 /* 32bit */ 303 #define D30IP_PIP 0 /* PCI Bridge Pin */ 304 #define D29IP 0x3108 /* 32bit */ 305 #define D29IP_E1P 0 /* EHCI #1 Pin */ 306 #define D28IP 0x310c /* 32bit */ 307 #define D28IP_P8IP 28 /* PCI Express Port 8 */ 308 #define D28IP_P7IP 24 /* PCI Express Port 7 */ 309 #define D28IP_P6IP 20 /* PCI Express Port 6 */ 310 #define D28IP_P5IP 16 /* PCI Express Port 5 */ 311 #define D28IP_P4IP 12 /* PCI Express Port 4 */ 312 #define D28IP_P3IP 8 /* PCI Express Port 3 */ 313 #define D28IP_P2IP 4 /* PCI Express Port 2 */ 314 #define D28IP_P1IP 0 /* PCI Express Port 1 */ 315 #define D27IP 0x3110 /* 32bit */ 316 #define D27IP_ZIP 0 /* HD Audio Pin */ 317 #define D26IP 0x3114 /* 32bit */ 318 #define D26IP_E2P 0 /* EHCI #2 Pin */ 319 #define D25IP 0x3118 /* 32bit */ 320 #define D25IP_LIP 0 /* GbE LAN Pin */ 321 #define D22IP 0x3124 /* 32bit */ 322 #define D22IP_KTIP 12 /* KT Pin */ 323 #define D22IP_IDERIP 8 /* IDE-R Pin */ 324 #define D22IP_MEI2IP 4 /* MEI #2 Pin */ 325 #define D22IP_MEI1IP 0 /* MEI #1 Pin */ 326 #define D20IP 0x3128 /* 32bit */ 327 #define D20IP_XHCIIP 0 328 #define D31IR 0x3140 /* 16bit */ 329 #define D30IR 0x3142 /* 16bit */ 330 #define D29IR 0x3144 /* 16bit */ 331 #define D28IR 0x3146 /* 16bit */ 332 #define D27IR 0x3148 /* 16bit */ 333 #define D26IR 0x314c /* 16bit */ 334 #define D25IR 0x3150 /* 16bit */ 335 #define D22IR 0x315c /* 16bit */ 336 #define D20IR 0x3160 /* 16bit */ 337 #define OIC 0x31fe /* 16bit */ 338 339 #define SPI_FREQ_SWSEQ 0x3893 340 #define SPI_DESC_COMP0 0x38b0 341 #define SPI_FREQ_WR_ERA 0x38b4 342 #define SOFT_RESET_CTRL 0x38f4 343 #define SOFT_RESET_DATA 0x38f8 344 345 #define DIR_ROUTE(a, b, c, d) \ 346 (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ 347 ((b) << DIR_IBR) | ((a) << DIR_IAR)) 348 349 #define RC 0x3400 /* 32bit */ 350 #define HPTC 0x3404 /* 32bit */ 351 #define GCS 0x3410 /* 32bit */ 352 #define BUC 0x3414 /* 32bit */ 353 #define PCH_DISABLE_GBE (1 << 5) 354 #define FD 0x3418 /* 32bit */ 355 #define DISPBDF 0x3424 /* 16bit */ 356 #define FD2 0x3428 /* 32bit */ 357 #define CG 0x341c /* 32bit */ 358 359 /* Function Disable 1 RCBA 0x3418 */ 360 #define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)) 361 #define PCH_DISABLE_P2P (1 << 1) 362 #define PCH_DISABLE_SATA1 (1 << 2) 363 #define PCH_DISABLE_SMBUS (1 << 3) 364 #define PCH_DISABLE_HD_AUDIO (1 << 4) 365 #define PCH_DISABLE_EHCI2 (1 << 13) 366 #define PCH_DISABLE_LPC (1 << 14) 367 #define PCH_DISABLE_EHCI1 (1 << 15) 368 #define PCH_DISABLE_PCIE(x) (1 << (16 + x)) 369 #define PCH_DISABLE_THERMAL (1 << 24) 370 #define PCH_DISABLE_SATA2 (1 << 25) 371 #define PCH_DISABLE_XHCI (1 << 27) 372 373 /* Function Disable 2 RCBA 0x3428 */ 374 #define PCH_DISABLE_KT (1 << 4) 375 #define PCH_DISABLE_IDER (1 << 3) 376 #define PCH_DISABLE_MEI2 (1 << 2) 377 #define PCH_DISABLE_MEI1 (1 << 1) 378 #define PCH_ENABLE_DBDF (1 << 0) 379 380 /* ICH7 GPIOBASE */ 381 #define GPIO_USE_SEL 0x00 382 #define GP_IO_SEL 0x04 383 #define GP_LVL 0x0c 384 #define GPO_BLINK 0x18 385 #define GPI_INV 0x2c 386 #define GPIO_USE_SEL2 0x30 387 #define GP_IO_SEL2 0x34 388 #define GP_LVL2 0x38 389 #define GPIO_USE_SEL3 0x40 390 #define GP_IO_SEL3 0x44 391 #define GP_LVL3 0x48 392 #define GP_RST_SEL1 0x60 393 #define GP_RST_SEL2 0x64 394 #define GP_RST_SEL3 0x68 395 396 /* ICH7 PMBASE */ 397 #define PM1_STS 0x00 398 #define WAK_STS (1 << 15) 399 #define PCIEXPWAK_STS (1 << 14) 400 #define PRBTNOR_STS (1 << 11) 401 #define RTC_STS (1 << 10) 402 #define PWRBTN_STS (1 << 8) 403 #define GBL_STS (1 << 5) 404 #define BM_STS (1 << 4) 405 #define TMROF_STS (1 << 0) 406 #define PM1_EN 0x02 407 #define PCIEXPWAK_DIS (1 << 14) 408 #define RTC_EN (1 << 10) 409 #define PWRBTN_EN (1 << 8) 410 #define GBL_EN (1 << 5) 411 #define TMROF_EN (1 << 0) 412 #define PM1_CNT 0x04 413 #define SLP_EN (1 << 13) 414 #define SLP_TYP (7 << 10) 415 #define SLP_TYP_S0 0 416 #define SLP_TYP_S1 1 417 #define SLP_TYP_S3 5 418 #define SLP_TYP_S4 6 419 #define SLP_TYP_S5 7 420 #define GBL_RLS (1 << 2) 421 #define BM_RLD (1 << 1) 422 #define SCI_EN (1 << 0) 423 #define PM1_TMR 0x08 424 #define PROC_CNT 0x10 425 #define LV2 0x14 426 #define LV3 0x15 427 #define LV4 0x16 428 #define PM2_CNT 0x50 /* mobile only */ 429 #define GPE0_STS 0x20 430 #define PME_B0_STS (1 << 13) 431 #define PME_STS (1 << 11) 432 #define BATLOW_STS (1 << 10) 433 #define PCI_EXP_STS (1 << 9) 434 #define RI_STS (1 << 8) 435 #define SMB_WAK_STS (1 << 7) 436 #define TCOSCI_STS (1 << 6) 437 #define SWGPE_STS (1 << 2) 438 #define HOT_PLUG_STS (1 << 1) 439 #define GPE0_EN 0x28 440 #define PME_B0_EN (1 << 13) 441 #define PME_EN (1 << 11) 442 #define TCOSCI_EN (1 << 6) 443 #define SMI_EN 0x30 444 #define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */ 445 #define LEGACY_USB2_EN (1 << 17) /* Legacy USB2 SMI logic */ 446 #define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */ 447 #define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */ 448 #define MCSMI_EN (1 << 11) /* Trap microcontroller range access */ 449 #define BIOS_RLS (1 << 7) /* asserts SCI on bit set */ 450 #define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */ 451 #define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */ 452 #define SLP_SMI_EN (1 << 4) /* Write SLP_EN in PM1_CNT asserts SMI# */ 453 #define LEGACY_USB_EN (1 << 3) /* Legacy USB circuit SMI logic */ 454 #define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */ 455 #define EOS (1 << 1) /* End of SMI (deassert SMI#) */ 456 #define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */ 457 #define SMI_STS 0x34 458 #define ALT_GP_SMI_EN 0x38 459 #define ALT_GP_SMI_STS 0x3a 460 #define GPE_CNTL 0x42 461 #define DEVACT_STS 0x44 462 #define SS_CNT 0x50 463 #define C3_RES 0x54 464 #define TCO1_STS 0x64 465 #define DMISCI_STS (1 << 9) 466 #define TCO2_STS 0x66 467 468 /** 469 * pch_silicon_revision() - Read silicon device ID from the PCH 470 * 471 * @dev: PCH device 472 * @return silicon device ID 473 */ 474 int pch_silicon_type(struct udevice *dev); 475 476 /** 477 * pch_pch_iobp_update() - Update a pch register 478 * 479 * @dev: PCH device 480 * @address: Address to update 481 * @andvalue: Value to AND with existing value 482 * @orvalue: Value to OR with existing value 483 */ 484 void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue, 485 u32 orvalue); 486 487 #endif 488