1 /*
2  * From Coreboot file of the same name
3  *
4  * Copyright (C) 2011 The ChromiumOS Authors.
5  *
6  * SPDX-License-Identifier:	GPL-2.0
7  */
8 
9 #ifndef _ASM_ARCH_MODEL_206AX_H
10 #define _ASM_ARCH_MODEL_206AX_H
11 
12 /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
13 #define SANDYBRIDGE_BCLK		100
14 
15 #define  CPUID_VMX			(1 << 5)
16 #define  CPUID_SMX			(1 << 6)
17 #define MSR_FEATURE_CONFIG		0x13c
18 #define MSR_FLEX_RATIO			0x194
19 #define  FLEX_RATIO_LOCK		(1 << 20)
20 #define  FLEX_RATIO_EN			(1 << 16)
21 #define IA32_PLATFORM_DCA_CAP		0x1f8
22 #define IA32_MISC_ENABLE		0x1a0
23 #define MSR_TEMPERATURE_TARGET		0x1a2
24 #define IA32_PERF_CTL			0x199
25 #define IA32_THERM_INTERRUPT		0x19b
26 #define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
27 #define  ENERGY_POLICY_PERFORMANCE	0
28 #define  ENERGY_POLICY_NORMAL		6
29 #define  ENERGY_POLICY_POWERSAVE	15
30 #define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
31 #define MSR_LT_LOCK_MEMORY		0x2e7
32 #define IA32_MC0_STATUS		0x401
33 
34 #define MSR_PIC_MSG_CONTROL		0x2e
35 #define  PLATFORM_INFO_SET_TDP		(1 << 29)
36 
37 #define MSR_MISC_PWR_MGMT		0x1aa
38 #define  MISC_PWR_MGMT_EIST_HW_DIS	(1 << 0)
39 #define MSR_TURBO_RATIO_LIMIT		0x1ad
40 #define MSR_POWER_CTL			0x1fc
41 
42 #define MSR_PKGC3_IRTL			0x60a
43 #define MSR_PKGC6_IRTL			0x60b
44 #define MSR_PKGC7_IRTL			0x60c
45 #define  IRTL_VALID			(1 << 15)
46 #define  IRTL_1_NS			(0 << 10)
47 #define  IRTL_32_NS			(1 << 10)
48 #define  IRTL_1024_NS			(2 << 10)
49 #define  IRTL_32768_NS			(3 << 10)
50 #define  IRTL_1048576_NS		(4 << 10)
51 #define  IRTL_33554432_NS		(5 << 10)
52 #define  IRTL_RESPONSE_MASK		(0x3ff)
53 
54 /* long duration in low dword, short duration in high dword */
55 #define  PKG_POWER_LIMIT_MASK		0x7fff
56 #define  PKG_POWER_LIMIT_EN		(1 << 15)
57 #define  PKG_POWER_LIMIT_CLAMP		(1 << 16)
58 #define  PKG_POWER_LIMIT_TIME_SHIFT	17
59 #define  PKG_POWER_LIMIT_TIME_MASK	0x7f
60 
61 #define MSR_PP0_CURRENT_CONFIG		0x601
62 #define  PP0_CURRENT_LIMIT		(112 << 3) /* 112 A */
63 #define MSR_PP1_CURRENT_CONFIG		0x602
64 #define  PP1_CURRENT_LIMIT_SNB		(35 << 3) /* 35 A */
65 #define  PP1_CURRENT_LIMIT_IVB		(50 << 3) /* 50 A */
66 #define MSR_PKG_POWER_SKU_UNIT		0x606
67 #define MSR_PKG_POWER_SKU		0x614
68 
69 #define IVB_CONFIG_TDP_MIN_CPUID	0x306a2
70 #define MSR_CONFIG_TDP_NOMINAL		0x648
71 #define MSR_CONFIG_TDP_LEVEL1		0x649
72 #define MSR_CONFIG_TDP_LEVEL2		0x64a
73 #define MSR_CONFIG_TDP_CONTROL		0x64b
74 #define MSR_TURBO_ACTIVATION_RATIO	0x64c
75 
76 /* P-state configuration */
77 #define PSS_MAX_ENTRIES			8
78 #define PSS_RATIO_STEP			2
79 #define PSS_LATENCY_TRANSITION		10
80 #define PSS_LATENCY_BUSMASTER		10
81 
82 #endif
83