1 /*
2  * From Coreboot src/southbridge/intel/bd82x6x/me.h
3  *
4  * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
5  *
6  * SPDX-License-Identifier:	GPL-2.0
7  */
8 
9 #ifndef _ASM_INTEL_ME_H
10 #define _ASM_INTEL_ME_H
11 
12 #include <linux/compiler.h>
13 #include <linux/types.h>
14 
15 #define ME_RETRY		100000	/* 1 second */
16 #define ME_DELAY		10	/* 10 us */
17 
18 /*
19  * Management Engine PCI registers
20  */
21 
22 #define PCI_CPU_MEBASE_L	0x70	/* Set by MRC */
23 #define PCI_CPU_MEBASE_H	0x74	/* Set by MRC */
24 
25 #define PCI_ME_HFS		0x40
26 #define  ME_HFS_CWS_RESET	0
27 #define  ME_HFS_CWS_INIT	1
28 #define  ME_HFS_CWS_REC		2
29 #define  ME_HFS_CWS_NORMAL	5
30 #define  ME_HFS_CWS_WAIT	6
31 #define  ME_HFS_CWS_TRANS	7
32 #define  ME_HFS_CWS_INVALID	8
33 #define  ME_HFS_STATE_PREBOOT	0
34 #define  ME_HFS_STATE_M0_UMA	1
35 #define  ME_HFS_STATE_M3	4
36 #define  ME_HFS_STATE_M0	5
37 #define  ME_HFS_STATE_BRINGUP	6
38 #define  ME_HFS_STATE_ERROR	7
39 #define  ME_HFS_ERROR_NONE	0
40 #define  ME_HFS_ERROR_UNCAT	1
41 #define  ME_HFS_ERROR_IMAGE	3
42 #define  ME_HFS_ERROR_DEBUG	4
43 #define  ME_HFS_MODE_NORMAL	0
44 #define  ME_HFS_MODE_DEBUG	2
45 #define  ME_HFS_MODE_DIS	3
46 #define  ME_HFS_MODE_OVER_JMPR	4
47 #define  ME_HFS_MODE_OVER_MEI	5
48 #define  ME_HFS_BIOS_DRAM_ACK	1
49 #define  ME_HFS_ACK_NO_DID	0
50 #define  ME_HFS_ACK_RESET	1
51 #define  ME_HFS_ACK_PWR_CYCLE	2
52 #define  ME_HFS_ACK_S3		3
53 #define  ME_HFS_ACK_S4		4
54 #define  ME_HFS_ACK_S5		5
55 #define  ME_HFS_ACK_GBL_RESET	6
56 #define  ME_HFS_ACK_CONTINUE	7
57 
58 struct me_hfs {
59 	u32 working_state:4;
60 	u32 mfg_mode:1;
61 	u32 fpt_bad:1;
62 	u32 operation_state:3;
63 	u32 fw_init_complete:1;
64 	u32 ft_bup_ld_flr:1;
65 	u32 update_in_progress:1;
66 	u32 error_code:4;
67 	u32 operation_mode:4;
68 	u32 reserved:4;
69 	u32 boot_options_present:1;
70 	u32 ack_data:3;
71 	u32 bios_msg_ack:4;
72 } __packed;
73 
74 #define PCI_ME_UMA		0x44
75 
76 struct me_uma {
77 	u32 size:6;
78 	u32 reserved_1:10;
79 	u32 valid:1;
80 	u32 reserved_0:14;
81 	u32 set_to_one:1;
82 } __packed;
83 
84 #define PCI_ME_H_GS		0x4c
85 #define  ME_INIT_DONE		1
86 #define  ME_INIT_STATUS_SUCCESS	0
87 #define  ME_INIT_STATUS_NOMEM	1
88 #define  ME_INIT_STATUS_ERROR	2
89 
90 struct me_did {
91 	u32 uma_base:16;
92 	u32 reserved:8;
93 	u32 status:4;
94 	u32 init_done:4;
95 } __packed;
96 
97 #define PCI_ME_GMES		0x48
98 #define  ME_GMES_PHASE_ROM	0
99 #define  ME_GMES_PHASE_BUP	1
100 #define  ME_GMES_PHASE_UKERNEL	2
101 #define  ME_GMES_PHASE_POLICY	3
102 #define  ME_GMES_PHASE_MODULE	4
103 #define  ME_GMES_PHASE_UNKNOWN	5
104 #define  ME_GMES_PHASE_HOST	6
105 
106 struct me_gmes {
107 	u32 bist_in_prog:1;
108 	u32 icc_prog_sts:2;
109 	u32 invoke_mebx:1;
110 	u32 cpu_replaced_sts:1;
111 	u32 mbp_rdy:1;
112 	u32 mfs_failure:1;
113 	u32 warm_rst_req_for_df:1;
114 	u32 cpu_replaced_valid:1;
115 	u32 reserved_1:2;
116 	u32 fw_upd_ipu:1;
117 	u32 reserved_2:4;
118 	u32 current_state:8;
119 	u32 current_pmevent:4;
120 	u32 progress_code:4;
121 } __packed;
122 
123 #define PCI_ME_HERES		0xbc
124 #define  PCI_ME_EXT_SHA1	0x00
125 #define  PCI_ME_EXT_SHA256	0x02
126 #define PCI_ME_HER(x)		(0xc0+(4*(x)))
127 
128 struct me_heres {
129 	u32 extend_reg_algorithm:4;
130 	u32 reserved:26;
131 	u32 extend_feature_present:1;
132 	u32 extend_reg_valid:1;
133 } __packed;
134 
135 /*
136  * Management Engine MEI registers
137  */
138 
139 #define MEI_H_CB_WW		0x00
140 #define MEI_H_CSR		0x04
141 #define MEI_ME_CB_RW		0x08
142 #define MEI_ME_CSR_HA		0x0c
143 
144 struct mei_csr {
145 	u32 interrupt_enable:1;
146 	u32 interrupt_status:1;
147 	u32 interrupt_generate:1;
148 	u32 ready:1;
149 	u32 reset:1;
150 	u32 reserved:3;
151 	u32 buffer_read_ptr:8;
152 	u32 buffer_write_ptr:8;
153 	u32 buffer_depth:8;
154 } __packed;
155 
156 #define MEI_ADDRESS_CORE	0x01
157 #define MEI_ADDRESS_AMT		0x02
158 #define MEI_ADDRESS_RESERVED	0x03
159 #define MEI_ADDRESS_WDT		0x04
160 #define MEI_ADDRESS_MKHI	0x07
161 #define MEI_ADDRESS_ICC		0x08
162 #define MEI_ADDRESS_THERMAL	0x09
163 
164 #define MEI_HOST_ADDRESS	0
165 
166 struct mei_header {
167 	u32 client_address:8;
168 	u32 host_address:8;
169 	u32 length:9;
170 	u32 reserved:6;
171 	u32 is_complete:1;
172 } __packed;
173 
174 #define MKHI_GROUP_ID_CBM	0x00
175 #define MKHI_GROUP_ID_FWCAPS	0x03
176 #define MKHI_GROUP_ID_MDES	0x08
177 #define MKHI_GROUP_ID_GEN	0xff
178 
179 #define MKHI_GLOBAL_RESET	0x0b
180 
181 #define MKHI_FWCAPS_GET_RULE	0x02
182 
183 #define MKHI_MDES_ENABLE	0x09
184 
185 #define MKHI_GET_FW_VERSION	0x02
186 #define MKHI_END_OF_POST	0x0c
187 #define MKHI_FEATURE_OVERRIDE	0x14
188 
189 struct mkhi_header {
190 	u32 group_id:8;
191 	u32 command:7;
192 	u32 is_response:1;
193 	u32 reserved:8;
194 	u32 result:8;
195 } __packed;
196 
197 struct me_fw_version {
198 	u16 code_minor;
199 	u16 code_major;
200 	u16 code_build_number;
201 	u16 code_hot_fix;
202 	u16 recovery_minor;
203 	u16 recovery_major;
204 	u16 recovery_build_number;
205 	u16 recovery_hot_fix;
206 } __packed;
207 
208 
209 #define HECI_EOP_STATUS_SUCCESS       0x0
210 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
211 
212 #define CBM_RR_GLOBAL_RESET	0x01
213 
214 #define GLOBAL_RESET_BIOS_MRC	0x01
215 #define GLOBAL_RESET_BIOS_POST	0x02
216 #define GLOBAL_RESET_MEBX	0x03
217 
218 struct me_global_reset {
219 	u8 request_origin;
220 	u8 reset_type;
221 } __packed;
222 
223 enum me_bios_path {
224 	ME_NORMAL_BIOS_PATH,
225 	ME_S3WAKE_BIOS_PATH,
226 	ME_ERROR_BIOS_PATH,
227 	ME_RECOVERY_BIOS_PATH,
228 	ME_DISABLE_BIOS_PATH,
229 	ME_FIRMWARE_UPDATE_BIOS_PATH,
230 };
231 
232 struct __packed mbp_fw_version_name {
233 	u32 major_version:16;
234 	u32 minor_version:16;
235 	u32 hotfix_version:16;
236 	u32 build_version:16;
237 };
238 
239 struct __packed mbp_icc_profile {
240 	u8 num_icc_profiles;
241 	u8 icc_profile_soft_strap;
242 	u8 icc_profile_index;
243 	u8 reserved;
244 	u32 register_lock_mask[3];
245 };
246 
247 struct __packed mefwcaps_sku {
248 	u32 full_net:1;
249 	u32 std_net:1;
250 	u32 manageability:1;
251 	u32 small_business:1;
252 	u32 l3manageability:1;
253 	u32 intel_at:1;
254 	u32 intel_cls:1;
255 	u32 reserved:3;
256 	u32 intel_mpc:1;
257 	u32 icc_over_clocking:1;
258 	u32 pavp:1;
259 	u32 reserved_1:4;
260 	u32 ipv6:1;
261 	u32 kvm:1;
262 	u32 och:1;
263 	u32 vlan:1;
264 	u32 tls:1;
265 	u32 reserved_4:1;
266 	u32 wlan:1;
267 	u32 reserved_5:8;
268 };
269 
270 struct __packed tdt_state_flag {
271 	u16 lock_state:1;
272 	u16 authenticate_module:1;
273 	u16 s3authentication:1;
274 	u16 flash_wear_out:1;
275 	u16 flash_variable_security:1;
276 	u16 wwan3gpresent:1;
277 	u16 wwan3goob:1;
278 	u16 reserved:9;
279 };
280 
281 struct __packed tdt_state_info {
282 	u8 state;
283 	u8 last_theft_trigger;
284 	struct tdt_state_flag flags;
285 };
286 
287 struct __packed platform_type_rule_data {
288 	u32 platform_target_usage_type:4;
289 	u32 platform_target_market_type:2;
290 	u32 super_sku:1;
291 	u32 reserved:1;
292 	u32 intel_me_fw_image_type:4;
293 	u32 platform_brand:4;
294 	u32 reserved_1:16;
295 };
296 
297 struct __packed mbp_fw_caps {
298 	struct mefwcaps_sku fw_capabilities;
299 	u8 available;
300 };
301 
302 struct __packed mbp_rom_bist_data {
303 	u16 device_id;
304 	u16 fuse_test_flags;
305 	u32 umchid[4];
306 };
307 
308 struct __packed mbp_platform_key {
309 	u32 key[8];
310 };
311 
312 struct __packed mbp_plat_type {
313 	struct platform_type_rule_data rule_data;
314 	u8 available;
315 };
316 
317 struct __packed me_bios_payload {
318 	struct mbp_fw_version_name fw_version_name;
319 	struct mbp_fw_caps fw_caps_sku;
320 	struct mbp_rom_bist_data rom_bist_data;
321 	struct mbp_platform_key platform_key;
322 	struct mbp_plat_type fw_plat_type;
323 	struct mbp_icc_profile icc_profile;
324 	struct tdt_state_info at_state;
325 	u32 mfsintegrity;
326 };
327 
328 struct __packed mbp_header {
329 	u32 mbp_size:8;
330 	u32 num_entries:8;
331 	u32 rsvd:16;
332 };
333 
334 struct __packed mbp_item_header {
335 	u32 app_id:8;
336 	u32 item_id:8;
337 	u32 length:8;
338 	u32 rsvd:8;
339 };
340 
341 struct __packed me_fwcaps {
342 	u32 id;
343 	u8 length;
344 	struct mefwcaps_sku caps_sku;
345 	u8 reserved[3];
346 };
347 
348 /* Defined in me_status.c for both romstage and ramstage */
349 void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes);
350 
351 void intel_early_me_status(void);
352 int intel_early_me_init(void);
353 int intel_early_me_uma_size(void);
354 int intel_early_me_init_done(u8 status);
355 
356 #endif
357