1 /* 2 * Copyright (c) 2016 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef __ASM_ARCH_PCH_H 8 #define __ASM_ARCH_PCH_H 9 10 /* CPU bus clock is fixed at 100MHz */ 11 #define CPU_BCLK 100 12 13 #define PMBASE 0x40 14 #define ACPI_CNTL 0x44 15 #define ACPI_EN (1 << 7) 16 17 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ 18 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ 19 #define GPIO_EN (1 << 4) 20 21 #define PCIEXBAR 0x60 22 23 #define PCH_DEV_LPC PCI_BDF(0, 0x1f, 0) 24 25 /* RCB registers */ 26 #define OIC 0x31fe /* 16bit */ 27 #define HPTC 0x3404 /* 32bit */ 28 #define FD 0x3418 /* 32bit */ 29 30 /* Function Disable 1 RCBA 0x3418 */ 31 #define PCH_DISABLE_ALWAYS (1 << 0) 32 33 /* PM registers */ 34 #define TCO1_CNT 0x60 35 #define TCO_TMR_HLT (1 << 11) 36 37 38 /* Device 0:0.0 PCI configuration space */ 39 40 #define EPBAR 0x40 41 #define MCHBAR 0x48 42 #define PCIEXBAR 0x60 43 #define DMIBAR 0x68 44 #define GGC 0x50 /* GMCH Graphics Control */ 45 #define DEVEN 0x54 /* Device Enable */ 46 #define DEVEN_D7EN (1 << 14) 47 #define DEVEN_D4EN (1 << 7) 48 #define DEVEN_D3EN (1 << 5) 49 #define DEVEN_D2EN (1 << 4) 50 #define DEVEN_D1F0EN (1 << 3) 51 #define DEVEN_D1F1EN (1 << 2) 52 #define DEVEN_D1F2EN (1 << 1) 53 #define DEVEN_D0EN (1 << 0) 54 #define DPR 0x5c 55 #define DPR_EPM (1 << 2) 56 #define DPR_PRS (1 << 1) 57 #define DPR_SIZE_MASK 0xff0 58 59 #define MCHBAR_PEI_VERSION 0x5034 60 #define BIOS_RESET_CPL 0x5da8 61 #define EDRAMBAR 0x5408 62 #define MCH_PAIR 0x5418 63 #define GDXCBAR 0x5420 64 65 #define PAM0 0x80 66 #define PAM1 0x81 67 #define PAM2 0x82 68 #define PAM3 0x83 69 #define PAM4 0x84 70 #define PAM5 0x85 71 #define PAM6 0x86 72 73 /* PCODE MMIO communications live in the MCHBAR. */ 74 #define BIOS_MAILBOX_INTERFACE 0x5da4 75 #define MAILBOX_RUN_BUSY (1 << 31) 76 #define MAILBOX_BIOS_CMD_READ_PCS 1 77 #define MAILBOX_BIOS_CMD_WRITE_PCS 2 78 #define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 79 #define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 80 #define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa 81 #define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb 82 #define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26 83 #define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27 84 /* Errors are returned back in bits 7:0. */ 85 #define MAILBOX_BIOS_ERROR_NONE 0 86 #define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 87 #define MAILBOX_BIOS_ERROR_TIMEOUT 2 88 #define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 89 #define MAILBOX_BIOS_ERROR_RESERVED 4 90 #define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 91 #define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 92 #define MAILBOX_BIOS_ERROR_VR_ERROR 7 93 /* Data is passed through bits 31:0 of the data register. */ 94 #define BIOS_MAILBOX_DATA 0x5da0 95 96 /* SATA IOBP Registers */ 97 #define SATA_IOBP_SP0_SECRT88 0xea002688 98 #define SATA_IOBP_SP1_SECRT88 0xea002488 99 100 #define SATA_SECRT88_VADJ_MASK 0xff 101 #define SATA_SECRT88_VADJ_SHIFT 16 102 103 #define SATA_IOBP_SP0DTLE_DATA 0xea002550 104 #define SATA_IOBP_SP0DTLE_EDGE 0xea002554 105 #define SATA_IOBP_SP1DTLE_DATA 0xea002750 106 #define SATA_IOBP_SP1DTLE_EDGE 0xea002754 107 108 #define SATA_DTLE_MASK 0xF 109 #define SATA_DTLE_DATA_SHIFT 24 110 #define SATA_DTLE_EDGE_SHIFT 16 111 112 /* Power Management */ 113 #define GEN_PMCON_1 0xa0 114 #define SMI_LOCK (1 << 4) 115 #define GEN_PMCON_2 0xa2 116 #define SYSTEM_RESET_STS (1 << 4) 117 #define THERMTRIP_STS (1 << 3) 118 #define SYSPWR_FLR (1 << 1) 119 #define PWROK_FLR (1 << 0) 120 #define GEN_PMCON_3 0xa4 121 #define SUS_PWR_FLR (1 << 14) 122 #define GEN_RST_STS (1 << 9) 123 #define RTC_BATTERY_DEAD (1 << 2) 124 #define PWR_FLR (1 << 1) 125 #define SLEEP_AFTER_POWER_FAIL (1 << 0) 126 #define GEN_PMCON_LOCK 0xa6 127 #define SLP_STR_POL_LOCK (1 << 2) 128 #define ACPI_BASE_LOCK (1 << 1) 129 #define PMIR 0xac 130 #define PMIR_CF9LOCK (1 << 31) 131 #define PMIR_CF9GR (1 << 20) 132 133 /* Broadwell PCH (Wildcat Point) */ 134 #define PCH_WPT_HSW_U_SAMPLE 0x9cc1 135 #define PCH_WPT_BDW_U_SAMPLE 0x9cc2 136 #define PCH_WPT_BDW_U_PREMIUM 0x9cc3 137 #define PCH_WPT_BDW_U_BASE 0x9cc5 138 #define PCH_WPT_BDW_Y_SAMPLE 0x9cc6 139 #define PCH_WPT_BDW_Y_PREMIUM 0x9cc7 140 #define PCH_WPT_BDW_Y_BASE 0x9cc9 141 #define PCH_WPT_BDW_H 0x9ccb 142 143 #define SA_IGD_OPROM_VENDEV 0x80860406 144 145 /* Dynamically determine if the part is ULT */ 146 bool cpu_is_ult(void); 147 148 u32 pch_iobp_read(u32 address); 149 int pch_iobp_write(u32 address, u32 data); 150 int pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); 151 int pch_iobp_exec(u32 addr, u16 op_dcode, u8 route_id, u32 *data, u8 *resp); 152 153 #endif 154