1 /* 2 * From coreboot soc/intel/broadwell/include/soc/me.h 3 * 4 * Copyright (C) 2014 Google Inc. 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #ifndef _asm_arch_me_h 10 #define _asm_arch_me_h 11 12 #include <asm/me_common.h> 13 14 #define ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */ 15 16 #define ME_HSIO_MESSAGE (7 << 28) 17 #define ME_HSIO_CMD_GETHSIOVER 1 18 #define ME_HSIO_CMD_CLOSE 0 19 20 /* 21 * Apparently the GMES register is renamed to HFS2 (or HFSTS2 according 22 * to ME9 BWG). Sadly the PCH EDS and the ME BWG do not match on nomenclature. 23 */ 24 #define PCI_ME_HFS2 0x48 25 /* Infrastructure Progress Values */ 26 #define ME_HFS2_PHASE_ROM 0 27 #define ME_HFS2_PHASE_BUP 1 28 #define ME_HFS2_PHASE_UKERNEL 2 29 #define ME_HFS2_PHASE_POLICY 3 30 #define ME_HFS2_PHASE_MODULE_LOAD 4 31 #define ME_HFS2_PHASE_UNKNOWN 5 32 #define ME_HFS2_PHASE_HOST_COMM 6 33 /* Current State - Based on Infra Progress values. */ 34 /* ROM State */ 35 #define ME_HFS2_STATE_ROM_BEGIN 0 36 #define ME_HFS2_STATE_ROM_DISABLE 6 37 /* BUP State */ 38 #define ME_HFS2_STATE_BUP_INIT 0 39 #define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1 40 #define ME_HFS2_STATE_BUP_FLOW_DET 4 41 #define ME_HFS2_STATE_BUP_VSCC_ERR 8 42 #define ME_HFS2_STATE_BUP_CHECK_STRAP 0xa 43 #define ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb 44 #define ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd 45 #define ME_HFS2_STATE_BUP_M3 0x11 46 #define ME_HFS2_STATE_BUP_M0 0x12 47 #define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13 48 #define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15 49 #define ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17 50 #define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18 51 #define ME_HFS2_STATE_BUP_T32_MISSING 0x1c 52 #define ME_HFS2_STATE_BUP_WAIT_DID 0x1f 53 #define ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20 54 #define ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21 55 #define ME_HFS2_STATE_BUP_ENABLE_UMA 0x22 56 #define ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23 57 #define ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24 58 #define ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25 59 #define ME_HFS2_STATE_BUP_M0_CLK 0x26 60 #define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27 61 #define ME_HFS2_STATE_BUP_TEMP_DIS 0x28 62 #define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32 63 /* Policy Module State */ 64 #define ME_HFS2_STATE_POLICY_ENTRY 0 65 #define ME_HFS2_STATE_POLICY_RCVD_S3 3 66 #define ME_HFS2_STATE_POLICY_RCVD_S4 4 67 #define ME_HFS2_STATE_POLICY_RCVD_S5 5 68 #define ME_HFS2_STATE_POLICY_RCVD_UPD 6 69 #define ME_HFS2_STATE_POLICY_RCVD_PCR 7 70 #define ME_HFS2_STATE_POLICY_RCVD_NPCR 8 71 #define ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9 72 #define ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa 73 #define ME_HFS2_STATE_POLICY_RCVD_DID 0xb 74 #define ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc 75 #define ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd 76 #define ME_HFS2_STATE_POLICY_FPB_ERR 0xe 77 #define ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf 78 #define ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10 79 /* Current PM Event Values */ 80 #define ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0 81 #define ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1 82 #define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2 83 #define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3 84 #define ME_HFS2_PMEVENT_CLEAN_ME_RESET 4 85 #define ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5 86 #define ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6 87 #define ME_HFS2_PMEVENT_S0MO_SXM3 7 88 #define ME_HFS2_PMEVENT_SXM3_S0M0 8 89 #define ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9 90 #define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa 91 #define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb 92 #define ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc 93 94 struct me_hfs2 { 95 u32 bist_in_progress:1; 96 u32 reserved1:2; 97 u32 invoke_mebx:1; 98 u32 cpu_replaced_sts:1; 99 u32 mbp_rdy:1; 100 u32 mfs_failure:1; 101 u32 warm_reset_request:1; 102 u32 cpu_replaced_valid:1; 103 u32 reserved2:4; 104 u32 mbp_cleared:1; 105 u32 reserved3:2; 106 u32 current_state:8; 107 u32 current_pmevent:4; 108 u32 progress_code:4; 109 } __packed; 110 111 #define PCI_ME_HFS5 0x68 112 113 #define PCI_ME_H_GS2 0x70 114 #define PCI_ME_MBP_GIVE_UP 0x01 115 116 /* ICC Messages */ 117 #define ICC_SET_CLOCK_ENABLES 0x3 118 #define ICC_API_VERSION_LYNXPOINT 0x00030000 119 120 struct icc_header { 121 u32 api_version; 122 u32 icc_command; 123 u32 icc_status; 124 u32 length; 125 u32 reserved; 126 } __packed; 127 128 struct icc_clock_enables_msg { 129 u32 clock_enables; 130 u32 clock_mask; 131 u32 no_response:1; 132 u32 reserved:31; 133 } __packed; 134 135 /* 136 * ME to BIOS Payload Datastructures and definitions. The ordering of the 137 * structures follows the ordering in the ME9 BWG. 138 */ 139 140 #define MBP_APPID_KERNEL 1 141 #define MBP_APPID_INTEL_AT 3 142 #define MBP_APPID_HWA 4 143 #define MBP_APPID_ICC 5 144 #define MBP_APPID_NFC 6 145 /* Kernel items: */ 146 #define MBP_KERNEL_FW_VER_ITEM 1 147 #define MBP_KERNEL_FW_CAP_ITEM 2 148 #define MBP_KERNEL_ROM_BIST_ITEM 3 149 #define MBP_KERNEL_PLAT_KEY_ITEM 4 150 #define MBP_KERNEL_FW_TYPE_ITEM 5 151 #define MBP_KERNEL_MFS_FAILURE_ITEM 6 152 #define MBP_KERNEL_PLAT_TIME_ITEM 7 153 /* Intel AT items: */ 154 #define MBP_INTEL_AT_STATE_ITEM 1 155 /* ICC Items: */ 156 #define MBP_ICC_PROFILE_ITEM 1 157 /* HWA Items: */ 158 #define MBP_HWA_REQUEST_ITEM 1 159 /* NFC Items: */ 160 #define MBP_NFC_SUPPORT_DATA_ITEM 1 161 162 #define MBP_MAKE_IDENT(appid, item) ((appid << 8) | item) 163 #define MBP_IDENT(appid, item) \ 164 MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM) 165 166 struct mbp_fw_version_name { 167 u32 major_version:16; 168 u32 minor_version:16; 169 u32 hotfix_version:16; 170 u32 build_version:16; 171 } __packed; 172 173 struct icc_address_mask { 174 u16 icc_start_address; 175 u16 mask; 176 } __packed; 177 178 struct mbp_icc_profile { 179 u8 num_icc_profiles; 180 u8 icc_profile_soft_strap; 181 u8 icc_profile_index; 182 u8 reserved; 183 u32 icc_reg_bundles; 184 struct icc_address_mask icc_address_mask[0]; 185 } __packed; 186 187 struct me_bios_payload { 188 struct mbp_fw_version_name *fw_version_name; 189 struct mbp_mefwcaps *fw_capabilities; 190 struct mbp_rom_bist_data *rom_bist_data; 191 struct mbp_platform_key *platform_key; 192 struct mbp_plat_type *fw_plat_type; 193 struct mbp_icc_profile *icc_profile; 194 struct mbp_at_state *at_state; 195 u32 *mfsintegrity; 196 struct mbp_plat_time *plat_time; 197 struct mbp_nfc_data *nfc_data; 198 }; 199 200 #endif 201