1 /* 2 * Copyright (c) 2016 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef __asm_arch_cpu_h 8 #define __asm_arch_cpu_h 9 10 /* CPU types */ 11 #define HASWELL_FAMILY_ULT 0x40650 12 #define BROADWELL_FAMILY_ULT 0x306d0 13 14 /* Supported CPUIDs */ 15 #define CPUID_HASWELL_A0 0x306c1 16 #define CPUID_HASWELL_B0 0x306c2 17 #define CPUID_HASWELL_C0 0x306c3 18 #define CPUID_HASWELL_ULT_B0 0x40650 19 #define CPUID_HASWELL_ULT 0x40651 20 #define CPUID_HASWELL_HALO 0x40661 21 #define CPUID_BROADWELL_C0 0x306d2 22 #define CPUID_BROADWELL_D0 0x306d3 23 #define CPUID_BROADWELL_E0 0x306d4 24 25 /* Broadwell bus clock is fixed at 100MHz */ 26 #define BROADWELL_BCLK 100 27 28 #define BROADWELL_FAMILY_ULT 0x306d0 29 30 #define CORE_THREAD_COUNT_MSR 0x35 31 32 #define MSR_VR_CURRENT_CONFIG 0x601 33 #define MSR_VR_MISC_CONFIG 0x603 34 #define MSR_PKG_POWER_SKU 0x614 35 #define MSR_DDR_RAPL_LIMIT 0x618 36 #define MSR_VR_MISC_CONFIG2 0x636 37 38 /* Latency times in units of 1024ns. */ 39 #define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42 40 #define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73 41 #define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91 42 #define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4 43 #define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145 44 #define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef 45 46 void cpu_set_power_limits(int power_limit_1_time); 47 48 #endif 49