1 /*
2  * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef _BRASWELL_IOMAP_H_
8 #define _BRASWELL_IOMAP_H_
9 
10 /* Memory Mapped IO bases */
11 
12 /* Power Management Controller */
13 #define PMC_BASE_ADDRESS	0xfed03000
14 #define PMC_BASE_SIZE		0x400
15 
16 /* Power Management Unit */
17 #define PUNIT_BASE_ADDRESS	0xfed05000
18 #define PUNIT_BASE_SIZE		0x800
19 
20 /* Intel Legacy Block */
21 #define ILB_BASE_ADDRESS	0xfed08000
22 #define ILB_BASE_SIZE		0x400
23 
24 /* SPI Bus */
25 #define SPI_BASE_ADDRESS	0xfed01000
26 #define SPI_BASE_SIZE		0x400
27 
28 /* Root Complex Base Address */
29 #define RCBA_BASE_ADDRESS	0xfed1c000
30 #define RCBA_BASE_SIZE		0x400
31 
32 /* IO Memory */
33 #define IO_BASE_ADDRESS		0xfed80000
34 #define IO_BASE_SIZE		0x4000
35 
36 /* MODPHY */
37 #define MPHY_BASE_ADDRESS	0xfef00000
38 #define MPHY_BASE_SIZE		0x100000
39 
40 /* IO Port bases */
41 
42 #define ACPI_BASE_ADDRESS	0x400
43 #define ACPI_BASE_SIZE		0x80
44 
45 #define GPIO_BASE_ADDRESS	0x500
46 #define GPIO_BASE_SIZE		0x100
47 
48 #define SMBUS_BASE_ADDRESS	0xefa0
49 
50 #endif /* _BRASWELL_IOMAP_H_ */
51