1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2de9ac9a1SBin Meng /* 3de9ac9a1SBin Meng * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> 4de9ac9a1SBin Meng */ 5de9ac9a1SBin Meng 6de9ac9a1SBin Meng #ifndef _BRASWELL_IOMAP_H_ 7de9ac9a1SBin Meng #define _BRASWELL_IOMAP_H_ 8de9ac9a1SBin Meng 9de9ac9a1SBin Meng /* Memory Mapped IO bases */ 10de9ac9a1SBin Meng 11de9ac9a1SBin Meng /* Power Management Controller */ 12de9ac9a1SBin Meng #define PMC_BASE_ADDRESS 0xfed03000 13de9ac9a1SBin Meng #define PMC_BASE_SIZE 0x400 14de9ac9a1SBin Meng 15de9ac9a1SBin Meng /* Power Management Unit */ 16de9ac9a1SBin Meng #define PUNIT_BASE_ADDRESS 0xfed05000 17de9ac9a1SBin Meng #define PUNIT_BASE_SIZE 0x800 18de9ac9a1SBin Meng 19de9ac9a1SBin Meng /* Intel Legacy Block */ 20de9ac9a1SBin Meng #define ILB_BASE_ADDRESS 0xfed08000 21de9ac9a1SBin Meng #define ILB_BASE_SIZE 0x400 22de9ac9a1SBin Meng 23de9ac9a1SBin Meng /* SPI Bus */ 24de9ac9a1SBin Meng #define SPI_BASE_ADDRESS 0xfed01000 25de9ac9a1SBin Meng #define SPI_BASE_SIZE 0x400 26de9ac9a1SBin Meng 27de9ac9a1SBin Meng /* Root Complex Base Address */ 28de9ac9a1SBin Meng #define RCBA_BASE_ADDRESS 0xfed1c000 29de9ac9a1SBin Meng #define RCBA_BASE_SIZE 0x400 30de9ac9a1SBin Meng 31de9ac9a1SBin Meng /* IO Memory */ 32de9ac9a1SBin Meng #define IO_BASE_ADDRESS 0xfed80000 33de9ac9a1SBin Meng #define IO_BASE_SIZE 0x4000 34de9ac9a1SBin Meng 35de9ac9a1SBin Meng /* MODPHY */ 36de9ac9a1SBin Meng #define MPHY_BASE_ADDRESS 0xfef00000 37de9ac9a1SBin Meng #define MPHY_BASE_SIZE 0x100000 38de9ac9a1SBin Meng 39de9ac9a1SBin Meng /* IO Port bases */ 40de9ac9a1SBin Meng 41de9ac9a1SBin Meng #define ACPI_BASE_ADDRESS 0x400 42de9ac9a1SBin Meng #define ACPI_BASE_SIZE 0x80 43de9ac9a1SBin Meng 44de9ac9a1SBin Meng #define GPIO_BASE_ADDRESS 0x500 45de9ac9a1SBin Meng #define GPIO_BASE_SIZE 0x100 46de9ac9a1SBin Meng 47de9ac9a1SBin Meng #define SMBUS_BASE_ADDRESS 0xefa0 48de9ac9a1SBin Meng 49de9ac9a1SBin Meng #endif /* _BRASWELL_IOMAP_H_ */ 50