1 /* 2 * Copyright (C) 2015, Intel Corporation 3 * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> 4 * 5 * SPDX-License-Identifier: Intel 6 */ 7 8 #ifndef __FSP_VPD_H__ 9 #define __FSP_VPD_H__ 10 11 struct __packed memory_upd { 12 u64 signature; /* Offset 0x0020 */ 13 u8 revision; /* Offset 0x0028 */ 14 u8 unused2[7]; /* Offset 0x0029 */ 15 u16 mrc_init_tseg_size; /* Offset 0x0030 */ 16 u16 mrc_init_mmio_size; /* Offset 0x0032 */ 17 u8 mrc_init_spd_addr1; /* Offset 0x0034 */ 18 u8 mrc_init_spd_addr2; /* Offset 0x0035 */ 19 u8 mem_ch0_config; /* Offset 0x0036 */ 20 u8 mem_ch1_config; /* Offset 0x0037 */ 21 u32 memory_spd_ptr; /* Offset 0x0038 */ 22 u8 igd_dvmt50_pre_alloc; /* Offset 0x003c */ 23 u8 aperture_size; /* Offset 0x003d */ 24 u8 gtt_size; /* Offset 0x003e */ 25 u8 legacy_seg_decode; /* Offset 0x003f */ 26 u8 enable_dvfs; /* Offset 0x0040 */ 27 u8 memory_type; /* Offset 0x0041 */ 28 u8 enable_ca_mirror; /* Offset 0x0042 */ 29 u8 reserved[189]; /* Offset 0x0043 */ 30 }; 31 32 struct __packed azalia_verb_table_header { 33 u32 vendor_device_id; 34 u16 sub_system_id; 35 u8 revision_id; 36 u8 front_panel_support; 37 u16 number_of_rear_jacks; 38 u16 number_of_front_jacks; 39 }; 40 41 struct __packed azalia_verb_table { 42 struct azalia_verb_table_header header; 43 u32 *data; 44 }; 45 46 struct __packed azalia_config { 47 u8 pme_enable:1; 48 u8 docking_supported:1; 49 u8 docking_attached:1; 50 u8 hdmi_codec_enable:1; 51 u8 azalia_v_ci_enable:1; 52 u8 reserved:3; 53 u8 verb_table_num; 54 struct azalia_verb_table *verb_table; 55 u16 reset_wait_timer_ms; 56 }; 57 58 struct gpio_family { 59 u32 confg; 60 u32 confg_changes; 61 u32 misc; 62 u32 mmio_addr; 63 wchar_t *name; 64 }; 65 66 struct gpio_pad { 67 u32 confg0; 68 u32 confg0_changes; 69 u32 confg1; 70 u32 confg1_changes; 71 u32 community; 72 u32 mmio_addr; 73 wchar_t *name; 74 u32 misc; 75 }; 76 77 struct __packed silicon_upd { 78 u64 signature; /* Offset 0x0100 */ 79 u8 revision; /* Offset 0x0108 */ 80 u8 unused3[7]; /* Offset 0x0109 */ 81 u8 sdcard_mode; /* Offset 0x0110 */ 82 u8 enable_hsuart0; /* Offset 0x0111 */ 83 u8 enable_hsuart1; /* Offset 0x0112 */ 84 u8 enable_azalia; /* Offset 0x0113 */ 85 struct azalia_config *azalia_cfg_ptr; /* Offset 0x0114 */ 86 u8 enable_sata; /* Offset 0x0118 */ 87 u8 enable_xhci; /* Offset 0x0119 */ 88 u8 lpe_mode; /* Offset 0x011a */ 89 u8 enable_dma0; /* Offset 0x011b */ 90 u8 enable_dma1; /* Offset 0x011c */ 91 u8 enable_i2c0; /* Offset 0x011d */ 92 u8 enable_i2c1; /* Offset 0x011e */ 93 u8 enable_i2c2; /* Offset 0x011f */ 94 u8 enable_i2c3; /* Offset 0x0120 */ 95 u8 enable_i2c4; /* Offset 0x0121 */ 96 u8 enable_i2c5; /* Offset 0x0122 */ 97 u8 enable_i2c6; /* Offset 0x0123 */ 98 u32 graphics_config_ptr; /* Offset 0x0124 */ 99 struct gpio_family *gpio_familiy_ptr; /* Offset 0x0128 */ 100 struct gpio_pad *gpio_pad_ptr; /* Offset 0x012c */ 101 u8 disable_punit_pwr_config; /* Offset 0x0130 */ 102 u8 chv_svid_config; /* Offset 0x0131 */ 103 u8 disable_dptf; /* Offset 0x0132 */ 104 u8 emmc_mode; /* Offset 0x0133 */ 105 u8 usb3_clk_ssc; /* Offset 0x0134 */ 106 u8 disp_clk_ssc; /* Offset 0x0135 */ 107 u8 sata_clk_ssc; /* Offset 0x0136 */ 108 u8 usb2_port0_pe_txi_set; /* Offset 0x0137 */ 109 u8 usb2_port0_txi_set; /* Offset 0x0138 */ 110 u8 usb2_port0_tx_emphasis_en; /* Offset 0x0139 */ 111 u8 usb2_port0_tx_pe_half; /* Offset 0x013a */ 112 u8 usb2_port1_pe_txi_set; /* Offset 0x013b */ 113 u8 usb2_port1_txi_set; /* Offset 0x013c */ 114 u8 usb2_port1_tx_emphasis_en; /* Offset 0x013d */ 115 u8 usb2_port1_tx_pe_half; /* Offset 0x013e */ 116 u8 usb2_port2_pe_txi_set; /* Offset 0x013f */ 117 u8 usb2_port2_txi_set; /* Offset 0x0140 */ 118 u8 usb2_port2_tx_emphasis_en; /* Offset 0x0141 */ 119 u8 usb2_port2_tx_pe_half; /* Offset 0x0142 */ 120 u8 usb2_port3_pe_txi_set; /* Offset 0x0143 */ 121 u8 usb2_port3_txi_set; /* Offset 0x0144 */ 122 u8 usb2_port3_tx_emphasis_en; /* Offset 0x0145 */ 123 u8 usb2_port3_tx_pe_half; /* Offset 0x0146 */ 124 u8 usb2_port4_pe_txi_set; /* Offset 0x0147 */ 125 u8 usb2_port4_txi_set; /* Offset 0x0148 */ 126 u8 usb2_port4_tx_emphasis_en; /* Offset 0x0149 */ 127 u8 usb2_port4_tx_pe_half; /* Offset 0x014a */ 128 u8 usb3_lane0_ow2tap_gen2_deemph3p5; /* Offset 0x014b */ 129 u8 usb3_lane1_ow2tap_gen2_deemph3p5; /* Offset 0x014c */ 130 u8 usb3_lane2_ow2tap_gen2_deemph3p5; /* Offset 0x014d */ 131 u8 usb3_lane3_ow2tap_gen2_deemph3p5; /* Offset 0x014e */ 132 u8 sata_speed; /* Offset 0x014f */ 133 u8 usb_ssic_port; /* Offset 0x0150 */ 134 u8 usb_hsic_port; /* Offset 0x0151 */ 135 u8 pcie_rootport_speed; /* Offset 0x0152 */ 136 u8 enable_ssic; /* Offset 0x0153 */ 137 u32 logo_ptr; /* Offset 0x0154 */ 138 u32 logo_size; /* Offset 0x0158 */ 139 u8 rtc_lock; /* Offset 0x015c */ 140 u8 pmic_i2c_bus; /* Offset 0x015d */ 141 u8 enable_isp; /* Offset 0x015e */ 142 u8 isp_pci_dev_config; /* Offset 0x015f */ 143 u8 turbo_mode; /* Offset 0x0160 */ 144 u8 pnp_settings; /* Offset 0x0161 */ 145 u8 sd_detect_chk; /* Offset 0x0162 */ 146 u8 reserved[411]; /* Offset 0x0163 */ 147 }; 148 149 #define MEMORY_UPD_ID 0x244450554d454d24 /* '$MEMUPD$' */ 150 #define SILICON_UPD_ID 0x244450555f495324 /* '$SI_UPD$' */ 151 152 struct __packed upd_region { 153 u64 signature; /* Offset 0x0000 */ 154 u8 revision; /* Offset 0x0008 */ 155 u8 unused0[7]; /* Offset 0x0009 */ 156 u32 memory_upd_offset; /* Offset 0x0010 */ 157 u32 silicon_upd_offset; /* Offset 0x0014 */ 158 u64 unused1; /* Offset 0x0018 */ 159 struct memory_upd memory_upd; /* Offset 0x0020 */ 160 struct silicon_upd silicon_upd; /* Offset 0x0100 */ 161 u16 terminator; /* Offset 0x02fe */ 162 }; 163 164 #define VPD_IMAGE_ID 0x2450534657534224 /* '$BSWFSP$' */ 165 166 struct __packed vpd_region { 167 u64 sign; /* Offset 0x0000 */ 168 u32 img_rev; /* Offset 0x0008 */ 169 u32 upd_offset; /* Offset 0x000c */ 170 }; 171 172 #endif /* __FSP_VPD_H__ */ 173