1*fffad926SBin Meng /* 2*fffad926SBin Meng * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> 3*fffad926SBin Meng * 4*fffad926SBin Meng * SPDX-License-Identifier: GPL-2.0+ 5*fffad926SBin Meng */ 6*fffad926SBin Meng 7*fffad926SBin Meng #ifndef __FSP_CONFIGS_H__ 8*fffad926SBin Meng #define __FSP_CONFIGS_H__ 9*fffad926SBin Meng 10*fffad926SBin Meng #ifndef __ASSEMBLY__ 11*fffad926SBin Meng struct fsp_config_data { 12*fffad926SBin Meng struct fsp_cfg_common common; 13*fffad926SBin Meng struct upd_region fsp_upd; 14*fffad926SBin Meng }; 15*fffad926SBin Meng 16*fffad926SBin Meng struct fspinit_rtbuf { 17*fffad926SBin Meng struct common_buf common; /* FSP common runtime data structure */ 18*fffad926SBin Meng }; 19*fffad926SBin Meng #endif 20*fffad926SBin Meng 21*fffad926SBin Meng /* FSP user configuration settings */ 22*fffad926SBin Meng 23*fffad926SBin Meng #define MRC_INIT_TSEG_SIZE_1MB 1 24*fffad926SBin Meng #define MRC_INIT_TSEG_SIZE_2MB 2 25*fffad926SBin Meng #define MRC_INIT_TSEG_SIZE_4MB 4 26*fffad926SBin Meng #define MRC_INIT_TSEG_SIZE_8MB 8 27*fffad926SBin Meng 28*fffad926SBin Meng #define MRC_INIT_MMIO_SIZE_1024MB 0x400 29*fffad926SBin Meng #define MRC_INIT_MMIO_SIZE_1536MB 0x600 30*fffad926SBin Meng #define MRC_INIT_MMIO_SIZE_2048MB 0x800 31*fffad926SBin Meng 32*fffad926SBin Meng #define IGD_DVMT50_PRE_ALLOC_32MB 0x01 33*fffad926SBin Meng #define IGD_DVMT50_PRE_ALLOC_64MB 0x02 34*fffad926SBin Meng #define IGD_DVMT50_PRE_ALLOC_96MB 0x03 35*fffad926SBin Meng #define IGD_DVMT50_PRE_ALLOC_128MB 0x04 36*fffad926SBin Meng #define IGD_DVMT50_PRE_ALLOC_160MB 0x05 37*fffad926SBin Meng #define IGD_DVMT50_PRE_ALLOC_192MB 0x06 38*fffad926SBin Meng #define IGD_DVMT50_PRE_ALLOC_224MB 0x07 39*fffad926SBin Meng #define IGD_DVMT50_PRE_ALLOC_256MB 0x08 40*fffad926SBin Meng #define IGD_DVMT50_PRE_ALLOC_288MB 0x09 41*fffad926SBin Meng #define IGD_DVMT50_PRE_ALLOC_320MB 0x0a 42*fffad926SBin Meng #define IGD_DVMT50_PRE_ALLOC_352MB 0x0b 43*fffad926SBin Meng #define IGD_DVMT50_PRE_ALLOC_384MB 0x0c 44*fffad926SBin Meng #define IGD_DVMT50_PRE_ALLOC_416MB 0x0d 45*fffad926SBin Meng #define IGD_DVMT50_PRE_ALLOC_448MB 0x0e 46*fffad926SBin Meng #define IGD_DVMT50_PRE_ALLOC_480MB 0x0f 47*fffad926SBin Meng #define IGD_DVMT50_PRE_ALLOC_512MB 0x10 48*fffad926SBin Meng 49*fffad926SBin Meng #define APERTURE_SIZE_128MB 1 50*fffad926SBin Meng #define APERTURE_SIZE_256MB 2 51*fffad926SBin Meng #define APERTURE_SIZE_512MB 3 52*fffad926SBin Meng 53*fffad926SBin Meng #define GTT_SIZE_1MB 1 54*fffad926SBin Meng #define GTT_SIZE_2MB 2 55*fffad926SBin Meng 56*fffad926SBin Meng #define DRAM_TYPE_DDR3 0 57*fffad926SBin Meng #define DRAM_TYPE_LPDDR3 1 58*fffad926SBin Meng 59*fffad926SBin Meng #define SDCARD_MODE_DISABLED 0 60*fffad926SBin Meng #define SDCARD_MODE_PCI 1 61*fffad926SBin Meng #define SDCARD_MODE_ACPI 2 62*fffad926SBin Meng 63*fffad926SBin Meng #define LPE_MODE_DISABLED 0 64*fffad926SBin Meng #define LPE_MODE_PCI 1 65*fffad926SBin Meng #define LPE_MODE_ACPI 2 66*fffad926SBin Meng 67*fffad926SBin Meng #define CHV_SVID_CONFIG_0 0 68*fffad926SBin Meng #define CHV_SVID_CONFIG_1 1 69*fffad926SBin Meng #define CHV_SVID_CONFIG_2 2 70*fffad926SBin Meng #define CHV_SVID_CONFIG_3 3 71*fffad926SBin Meng 72*fffad926SBin Meng #define EMMC_MODE_DISABLED 0 73*fffad926SBin Meng #define EMMC_MODE_PCI 1 74*fffad926SBin Meng #define EMMC_MODE_ACPI 2 75*fffad926SBin Meng 76*fffad926SBin Meng #define SATA_SPEED_GEN1 1 77*fffad926SBin Meng #define SATA_SPEED_GEN2 2 78*fffad926SBin Meng #define SATA_SPEED_GEN3 3 79*fffad926SBin Meng 80*fffad926SBin Meng #define ISP_PCI_DEV_CONFIG_1 1 81*fffad926SBin Meng #define ISP_PCI_DEV_CONFIG_2 2 82*fffad926SBin Meng #define ISP_PCI_DEV_CONFIG_3 3 83*fffad926SBin Meng 84*fffad926SBin Meng #define PNP_SETTING_DISABLED 0 85*fffad926SBin Meng #define PNP_SETTING_POWER 1 86*fffad926SBin Meng #define PNP_SETTING_PERF 2 87*fffad926SBin Meng #define PNP_SETTING_POWER_AND_PERF 3 88*fffad926SBin Meng 89*fffad926SBin Meng #endif /* __FSP_CONFIGS_H__ */ 90