1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 242f8ebfdSBin Meng /* 342f8ebfdSBin Meng * Copyright (C) 2013 Google Inc. 442f8ebfdSBin Meng * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> 542f8ebfdSBin Meng * 642f8ebfdSBin Meng * Modified from coreboot src/soc/intel/baytrail/include/soc/irq.h 742f8ebfdSBin Meng */ 842f8ebfdSBin Meng 942f8ebfdSBin Meng #ifndef _BAYTRAIL_IRQ_H_ 1042f8ebfdSBin Meng #define _BAYTRAIL_IRQ_H_ 1142f8ebfdSBin Meng 1242f8ebfdSBin Meng #define PIRQA_APIC_IRQ 16 1342f8ebfdSBin Meng #define PIRQB_APIC_IRQ 17 1442f8ebfdSBin Meng #define PIRQC_APIC_IRQ 18 1542f8ebfdSBin Meng #define PIRQD_APIC_IRQ 19 1642f8ebfdSBin Meng #define PIRQE_APIC_IRQ 20 1742f8ebfdSBin Meng #define PIRQF_APIC_IRQ 21 1842f8ebfdSBin Meng #define PIRQG_APIC_IRQ 22 1942f8ebfdSBin Meng #define PIRQH_APIC_IRQ 23 2042f8ebfdSBin Meng 2142f8ebfdSBin Meng /* The below IRQs are for when devices are in ACPI mode */ 2242f8ebfdSBin Meng #define LPE_DMA0_IRQ 24 2342f8ebfdSBin Meng #define LPE_DMA1_IRQ 25 2442f8ebfdSBin Meng #define LPE_SSP0_IRQ 26 2542f8ebfdSBin Meng #define LPE_SSP1_IRQ 27 2642f8ebfdSBin Meng #define LPE_SSP2_IRQ 28 2742f8ebfdSBin Meng #define LPE_IPC2HOST_IRQ 29 2842f8ebfdSBin Meng #define LPSS_I2C1_IRQ 32 2942f8ebfdSBin Meng #define LPSS_I2C2_IRQ 33 3042f8ebfdSBin Meng #define LPSS_I2C3_IRQ 34 3142f8ebfdSBin Meng #define LPSS_I2C4_IRQ 35 3242f8ebfdSBin Meng #define LPSS_I2C5_IRQ 36 3342f8ebfdSBin Meng #define LPSS_I2C6_IRQ 37 3442f8ebfdSBin Meng #define LPSS_I2C7_IRQ 38 3542f8ebfdSBin Meng #define LPSS_HSUART1_IRQ 39 3642f8ebfdSBin Meng #define LPSS_HSUART2_IRQ 40 3742f8ebfdSBin Meng #define LPSS_SPI_IRQ 41 3842f8ebfdSBin Meng #define LPSS_DMA1_IRQ 42 3942f8ebfdSBin Meng #define LPSS_DMA2_IRQ 43 4042f8ebfdSBin Meng #define SCC_EMMC_IRQ 44 4142f8ebfdSBin Meng #define SCC_SDIO_IRQ 46 4242f8ebfdSBin Meng #define SCC_SD_IRQ 47 4342f8ebfdSBin Meng #define GPIO_NC_IRQ 48 4442f8ebfdSBin Meng #define GPIO_SC_IRQ 49 4542f8ebfdSBin Meng #define GPIO_SUS_IRQ 50 4642f8ebfdSBin Meng /* GPIO direct / dedicated IRQs */ 4742f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_0 51 4842f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_1 52 4942f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_2 53 5042f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_3 54 5142f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_4 55 5242f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_5 56 5342f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_6 57 5442f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_7 58 5542f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_8 59 5642f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_9 60 5742f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_10 61 5842f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_11 62 5942f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_12 63 6042f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_13 64 6142f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_14 65 6242f8ebfdSBin Meng #define GPIO_S0_DED_IRQ_15 66 6342f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_0 67 6442f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_1 68 6542f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_2 69 6642f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_3 70 6742f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_4 71 6842f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_5 72 6942f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_6 73 7042f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_7 74 7142f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_8 75 7242f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_9 76 7342f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_10 77 7442f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_11 78 7542f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_12 79 7642f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_13 80 7742f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_14 81 7842f8ebfdSBin Meng #define GPIO_S5_DED_IRQ_15 82 7942f8ebfdSBin Meng /* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL */ 8042f8ebfdSBin Meng #define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot 8142f8ebfdSBin Meng #define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot 8242f8ebfdSBin Meng #define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot) 8342f8ebfdSBin Meng #define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot) 8442f8ebfdSBin Meng 8542f8ebfdSBin Meng #endif /* _BAYTRAIL_IRQ_H_ */ 86