1 /* 2 * Copyright (C) 2013 Google Inc. 3 * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> 4 * 5 * Modified from coreboot src/soc/intel/baytrail/include/soc/iomap.h 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _BAYTRAIL_IOMAP_H_ 11 #define _BAYTRAIL_IOMAP_H_ 12 13 /* Memory Mapped IO bases */ 14 15 /* PCI Configuration Space */ 16 #define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE 17 #define MCFG_BASE_SIZE 0x10000000 18 19 /* Temporary Base Address */ 20 #define TEMP_BASE_ADDRESS 0xfd000000 21 22 /* Transactions in this range will abort */ 23 #define ABORT_BASE_ADDRESS 0xfeb00000 24 #define ABORT_BASE_SIZE 0x00100000 25 26 /* High Performance Event Timer */ 27 #define HPET_BASE_ADDRESS 0xfed00000 28 #define HPET_BASE_SIZE 0x400 29 30 /* SPI Bus */ 31 #define SPI_BASE_ADDRESS 0xfed01000 32 #define SPI_BASE_SIZE 0x400 33 34 /* Power Management Controller */ 35 #define PMC_BASE_ADDRESS 0xfed03000 36 #define PMC_BASE_SIZE 0x400 37 38 #define GEN_PMCON1 0x20 39 #define UART_EN (1 << 24) 40 #define DISB (1 << 23) 41 #define MEM_SR (1 << 21) 42 #define SRS (1 << 20) 43 #define CTS (1 << 19) 44 #define MS4V (1 << 18) 45 #define PWR_FLR (1 << 16) 46 #define PME_B0_S5_DIS (1 << 15) 47 #define SUS_PWR_FLR (1 << 14) 48 #define WOL_EN_OVRD (1 << 13) 49 #define DIS_SLP_X_STRCH_SUS_UP (1 << 12) 50 #define GEN_RST_STS (1 << 9) 51 #define RPS (1 << 2) 52 #define AFTERG3_EN (1 << 0) 53 #define GEN_PMCON2 0x24 54 #define SLPSX_STR_POL_LOCK (1 << 18) 55 #define BIOS_PCI_EXP_EN (1 << 10) 56 #define PWRBTN_LVL (1 << 9) 57 #define SMI_LOCK (1 << 4) 58 59 /* Power Management Unit */ 60 #define PUNIT_BASE_ADDRESS 0xfed05000 61 #define PUNIT_BASE_SIZE 0x800 62 63 /* Intel Legacy Block */ 64 #define ILB_BASE_ADDRESS 0xfed08000 65 #define ILB_BASE_SIZE 0x400 66 67 /* IO Memory */ 68 #define IO_BASE_ADDRESS 0xfed0c000 69 #define IO_BASE_OFFSET_GPSCORE 0x0000 70 #define IO_BASE_OFFSET_GPNCORE 0x1000 71 #define IO_BASE_OFFSET_GPSSUS 0x2000 72 #define IO_BASE_SIZE 0x4000 73 74 /* Root Complex Base Address */ 75 #define RCBA_BASE_ADDRESS 0xfed1c000 76 #define RCBA_BASE_SIZE 0x400 77 78 /* MODPHY */ 79 #define MPHY_BASE_ADDRESS 0xfef00000 80 #define MPHY_BASE_SIZE 0x100000 81 82 /* IO Port bases */ 83 #define ACPI_BASE_ADDRESS 0x0400 84 #define ACPI_BASE_SIZE 0x80 85 86 #define PM1_STS 0x00 87 #define PM1_CNT 0x04 88 89 #define GPIO_BASE_ADDRESS 0x0500 90 #define GPIO_BASE_SIZE 0x100 91 92 #define SMBUS_BASE_ADDRESS 0xefa0 93 94 #endif /* _BAYTRAIL_IOMAP_H_ */ 95