1 /*
2  * Copyright (C) 2013, Intel Corporation
3  * Copyright (C) 2015 Google, Inc
4  *
5  * SPDX-License-Identifier:	Intel
6  */
7 
8 #ifndef __FSP_VPD_H
9 #define __FSP_VPD_H
10 
11 struct memory_down_data {
12 	uint8_t enable_memory_down;
13 	uint8_t dram_speed;
14 	uint8_t dram_type;
15 	uint8_t dimm_0_enable;
16 	uint8_t dimm_1_enable;
17 	uint8_t dimm_width;
18 	uint8_t dimm_density;
19 	uint8_t dimm_bus_width;
20 	uint8_t dimm_sides;			/* Ranks Per dimm_ */
21 	uint8_t dimm_tcl;			/* tCL */
22 	/* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
23 	uint8_t dimm_trpt_rcd;
24 	uint8_t dimm_twr;			/* tWR in DRAM clk  */
25 	uint8_t dimm_twtr;			/* tWTR in DRAM clk */
26 	uint8_t dimm_trrd;			/* tRRD in DRAM clk */
27 	uint8_t dimm_trtp;			/* tRTP in DRAM clk */
28 	uint8_t dimm_tfaw;			/* tFAW in DRAM clk */
29 };
30 
31 struct __packed upd_region {
32 	uint64_t signature;			/* Offset 0x0000 */
33 	uint8_t reserved0[24];			/* Offset 0x0008 */
34 	uint16_t mrc_init_tseg_size;		/* Offset 0x0020 */
35 	uint16_t mrc_init_mmio_size;		/* Offset 0x0022 */
36 	uint8_t mrc_init_spd_addr1;		/* Offset 0x0024 */
37 	uint8_t mrc_init_spd_addr2;		/* Offset 0x0025 */
38 	uint8_t emmc_boot_mode;			/* Offset 0x0026 */
39 	uint8_t enable_sdio;			/* Offset 0x0027 */
40 	uint8_t enable_sdcard;			/* Offset 0x0028 */
41 	uint8_t enable_hsuart0;			/* Offset 0x0029 */
42 	uint8_t enable_hsuart1;			/* Offset 0x002a */
43 	uint8_t enable_spi;			/* Offset 0x002b */
44 	uint8_t reserved1;			/* Offset 0x002c */
45 	uint8_t enable_sata;			/* Offset 0x002d */
46 	uint8_t sata_mode;			/* Offset 0x002e */
47 	uint8_t enable_azalia;			/* Offset 0x002f */
48 	uint32_t azalia_config_ptr;		/* Offset 0x0030 */
49 	uint8_t enable_xhci;			/* Offset 0x0034 */
50 	uint8_t enable_lpe;			/* Offset 0x0035 */
51 	uint8_t lpss_sio_enable_pci_mode;	/* Offset 0x0036 */
52 	uint8_t enable_dma0;			/* Offset 0x0037 */
53 	uint8_t enable_dma1;			/* Offset 0x0038 */
54 	uint8_t enable_i2_c0;			/* Offset 0x0039 */
55 	uint8_t enable_i2_c1;			/* Offset 0x003a */
56 	uint8_t enable_i2_c2;			/* Offset 0x003b */
57 	uint8_t enable_i2_c3;			/* Offset 0x003c */
58 	uint8_t enable_i2_c4;			/* Offset 0x003d */
59 	uint8_t enable_i2_c5;			/* Offset 0x003e */
60 	uint8_t enable_i2_c6;			/* Offset 0x003f */
61 	uint8_t enable_pwm0;			/* Offset 0x0040 */
62 	uint8_t enable_pwm1;			/* Offset 0x0041 */
63 	uint8_t enable_hsi;			/* Offset 0x0042 */
64 	uint8_t igd_dvmt50_pre_alloc;		/* Offset 0x0043 */
65 	uint8_t aperture_size;			/* Offset 0x0044 */
66 	uint8_t gtt_size;			/* Offset 0x0045 */
67 	uint32_t serial_debug_port_address;	/* Offset 0x0046 */
68 	uint8_t serial_debug_port_type;		/* Offset 0x004a */
69 	uint8_t mrc_debug_msg;			/* Offset 0x004b */
70 	uint8_t isp_enable;			/* Offset 0x004c */
71 	uint8_t scc_enable_pci_mode;		/* Offset 0x004d */
72 	uint8_t igd_render_standby;		/* Offset 0x004e */
73 	uint8_t txe_uma_enable;			/* Offset 0x004f */
74 	uint8_t os_selection;			/* Offset 0x0050 */
75 	uint8_t emmc45_ddr50_enabled;		/* Offset 0x0051 */
76 	uint8_t emmc45_hs200_enabled;		/* Offset 0x0052 */
77 	uint8_t emmc45_retune_timer_value;	/* Offset 0x0053 */
78 	uint8_t unused_upd_space1[156];		/* Offset 0x0054 */
79 	struct memory_down_data memory_params;	/* Offset 0x00f0 */
80 	uint16_t terminator;			/* Offset 0x0100 */
81 };
82 
83 #define VPD_IMAGE_ID		0x3157454956594C56	/* 'VLYVIEW1' */
84 #define VPD_IMAGE_REV		0x00000303
85 
86 struct __packed vpd_region {
87 	uint64_t sign;				/* Offset 0x0000 */
88 	uint32_t img_rev;			/* Offset 0x0008 */
89 	uint32_t upd_offset;			/* Offset 0x000c */
90 	uint8_t unused[16];			/* Offset 0x0010 */
91 	uint32_t fsp_res_memlen;		/* Offset 0x0020 */
92 	uint8_t platform_type;			/* Offset 0x0024 */
93 	uint8_t enable_secure_boot;		/* Offset 0x0025 */
94 };
95 #endif
96