1 /* 2 * Copyright (C) 2013 Google Inc. 3 * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> 4 * 5 * Modified from coreboot src/soc/intel/baytrail/include/soc/pci_devs.h 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _DEVICE_H_ 11 #define _DEVICE_H_ 12 13 /* 14 * Internal PCI device numbers within the SoC. 15 * 16 * Note it must start with 0x_ prefix, as the device number macro will be 17 * included in the ACPI ASL files (see irq_helper.h and irq_route.h). 18 */ 19 20 /* SoC transaction router */ 21 #define SOC_DEV 0x00 22 23 /* Graphics and Display */ 24 #define GFX_DEV 0x02 25 26 /* MIPI */ 27 #define MIPI_DEV 0x03 28 29 /* EMMC Port */ 30 #define EMMC_DEV 0x10 31 32 /* SDIO Port */ 33 #define SDIO_DEV 0x11 34 35 /* SD Port */ 36 #define SD_DEV 0x12 37 38 /* SATA */ 39 #define SATA_DEV 0x13 40 41 /* xHCI */ 42 #define XHCI_DEV 0x14 43 44 /* LPE Audio */ 45 #define LPE_DEV 0x15 46 47 /* OTG */ 48 #define OTG_DEV 0x16 49 50 /* MMC45 Port */ 51 #define MMC45_DEV 0x17 52 53 /* Serial IO 1 */ 54 #define SIO1_DEV 0x18 55 56 /* Trusted Execution Engine */ 57 #define TXE_DEV 0x1a 58 59 /* HD Audio */ 60 #define HDA_DEV 0x1b 61 62 /* PCIe Ports */ 63 #define PCIE_DEV 0x1c 64 65 /* EHCI */ 66 #define EHCI_DEV 0x1d 67 68 /* Serial IO 2 */ 69 #define SIO2_DEV 0x1e 70 71 /* Platform Controller Unit */ 72 #define PCU_DEV 0x1f 73 74 #endif /* _DEVICE_H_ */ 75