1/*
2 * Copyright (C) 2013 Google Inc.
3 * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
4 *
5 * Modified from coreboot src/soc/intel/baytrail/acpi/southcluster.asl
6 *
7 * SPDX-License-Identifier:	GPL-2.0+
8 */
9
10Device (PCI0)
11{
12	Name(_HID, EISAID("PNP0A08"))	/* PCIe */
13	Name(_CID, EISAID("PNP0A03"))	/* PCI */
14
15	Name(_ADR, 0)
16	Name(_BBN, 0)
17
18	Name(MCRS, ResourceTemplate()
19	{
20		/* Bus Numbers */
21		WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
22				0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
23
24		/* IO Region 0 */
25		WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
26				0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
27
28		/* PCI Config Space */
29		IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
30
31		/* IO Region 1 */
32		WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
33				0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
34
35		/* VGA memory (0xa0000-0xbffff) */
36		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
37				Cacheable, ReadWrite,
38				0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
39				0x00020000, , , ASEG)
40
41		/* OPROM reserved (0xc0000-0xc3fff) */
42		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
43				Cacheable, ReadWrite,
44				0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
45				0x00004000, , , OPR0)
46
47		/* OPROM reserved (0xc4000-0xc7fff) */
48		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
49				Cacheable, ReadWrite,
50				0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
51				0x00004000, , , OPR1)
52
53		/* OPROM reserved (0xc8000-0xcbfff) */
54		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
55				Cacheable, ReadWrite,
56				0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
57				0x00004000, , , OPR2)
58
59		/* OPROM reserved (0xcc000-0xcffff) */
60		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
61				Cacheable, ReadWrite,
62				0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
63				0x00004000, , , OPR3)
64
65		/* OPROM reserved (0xd0000-0xd3fff) */
66		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
67				Cacheable, ReadWrite,
68				0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
69				0x00004000, , , OPR4)
70
71		/* OPROM reserved (0xd4000-0xd7fff) */
72		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
73				Cacheable, ReadWrite,
74				0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
75				0x00004000, , , OPR5)
76
77		/* OPROM reserved (0xd8000-0xdbfff) */
78		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
79				Cacheable, ReadWrite,
80				0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
81				0x00004000, , , OPR6)
82
83		/* OPROM reserved (0xdc000-0xdffff) */
84		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
85				Cacheable, ReadWrite,
86				0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
87				0x00004000, , , OPR7)
88
89		/* BIOS Extension (0xe0000-0xe3fff) */
90		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
91				Cacheable, ReadWrite,
92				0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
93				0x00004000, , , ESG0)
94
95		/* BIOS Extension (0xe4000-0xe7fff) */
96		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
97				Cacheable, ReadWrite,
98				0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
99				0x00004000, , , ESG1)
100
101		/* BIOS Extension (0xe8000-0xebfff) */
102		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
103				Cacheable, ReadWrite,
104				0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
105				0x00004000, , , ESG2)
106
107		/* BIOS Extension (0xec000-0xeffff) */
108		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
109				Cacheable, ReadWrite,
110				0x00000000, 0x000ec000, 0x000effff, 0x00000000,
111				0x00004000, , , ESG3)
112
113		/* System BIOS (0xf0000-0xfffff) */
114		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
115				Cacheable, ReadWrite,
116				0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
117				0x00010000, , , FSEG)
118
119		/* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */
120		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
121				Cacheable, ReadWrite,
122				0x00000000, 0x00000000, 0x00000000, 0x00000000,
123				0x00000000, , , PMEM)
124
125		/* High PCI Memory Region */
126		QwordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
127				Cacheable, ReadWrite,
128				0x00000000, 0x00000000, 0x00000000, 0x00000000,
129				0x00000000, , , UMEM)
130	})
131
132	Method(_CRS, 0, Serialized)
133	{
134		/* Update PCI resource area */
135		CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
136		CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
137		CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
138
139		/*
140		 * Hardcode TOLM to 2GB for now as BayTrail FSP uses this value.
141		 *
142		 * TODO: for generic usage, read TOLM value from register, or
143		 * from global NVS (not implemented by U-Boot yet).
144		 */
145		Store(0x80000000, PMIN)
146		Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX)
147		Add(Subtract(PMAX, PMIN), 1, PLEN)
148
149		/* Update High PCI resource area */
150		CreateQwordField(MCRS, ^UMEM._MIN, UMIN)
151		CreateQwordField(MCRS, ^UMEM._MAX, UMAX)
152		CreateQwordField(MCRS, ^UMEM._LEN, ULEN)
153
154		/* Set base address to 48GB and allocate 16GB for PCI space */
155		Store(0xc00000000, UMIN)
156		Store(0x400000000, ULEN)
157		Add(UMIN, Subtract(ULEN, 1), UMAX)
158
159		Return (MCRS)
160	}
161
162	/* Device Resource Consumption */
163	Device (PDRC)
164	{
165		Name(_HID, EISAID("PNP0C02"))
166		Name(_UID, 1)
167
168		Name(PDRS, ResourceTemplate() {
169			Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
170			Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
171			Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
172			Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
173			Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE)
174			Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
175			Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
176			Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE)
177		})
178
179		/* Current Resource Settings */
180		Method(_CRS, 0, Serialized)
181		{
182			Return (PDRS)
183		}
184	}
185
186	Method(_OSC, 4)
187	{
188		/* Check for proper GUID */
189		If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
190			/* Let OS control everything */
191			Return (Arg3)
192		} Else {
193			/* Unrecognized UUID */
194			CreateDWordField(Arg3, 0, CDW1)
195			Or(CDW1, 4, CDW1)
196			Return (Arg3)
197		}
198	}
199
200	/* LPC Bridge 0:1f.0 */
201	#include "lpc.asl"
202
203	/* USB EHCI 0:1d.0 */
204	#include "usb.asl"
205
206	/* USB XHCI 0:14.0 */
207	#include "xhci.asl"
208
209	/* IRQ routing for each PCI device */
210	#include <asm/acpi/irqroute.asl>
211}
212