1/* 2 * Copyright (C) 2007-2009 coresystems GmbH 3 * Copyright (C) 2013 Google Inc. 4 * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> 5 * 6 * Modified from coreboot src/soc/intel/baytrail/acpi/lpc.asl 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11/* Intel LPC Bus Device - 0:1f.0 */ 12 13Device (LPCB) 14{ 15 Name(_ADR, 0x001f0000) 16 17 OperationRegion(LPC0, PCI_Config, 0x00, 0x100) 18 Field(LPC0, AnyAcc, NoLock, Preserve) { 19 Offset(0x08), 20 SRID, 8, 21 Offset(0x80), 22 C1EN, 1, 23 Offset(0x84) 24 } 25 26 #include "irqlinks.asl" 27 28 /* Firmware Hub */ 29 Device (FWH) 30 { 31 Name(_HID, EISAID("INT0800")) 32 Name(_CRS, ResourceTemplate() 33 { 34 Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) 35 }) 36 } 37 38 /* 8259 Interrupt Controller */ 39 Device (PIC) 40 { 41 Name(_HID, EISAID("PNP0000")) 42 Name(_CRS, ResourceTemplate() 43 { 44 IO(Decode16, 0x20, 0x20, 0x01, 0x02) 45 IO(Decode16, 0x24, 0x24, 0x01, 0x02) 46 IO(Decode16, 0x28, 0x28, 0x01, 0x02) 47 IO(Decode16, 0x2c, 0x2c, 0x01, 0x02) 48 IO(Decode16, 0x30, 0x30, 0x01, 0x02) 49 IO(Decode16, 0x34, 0x34, 0x01, 0x02) 50 IO(Decode16, 0x38, 0x38, 0x01, 0x02) 51 IO(Decode16, 0x3c, 0x3c, 0x01, 0x02) 52 IO(Decode16, 0xa0, 0xa0, 0x01, 0x02) 53 IO(Decode16, 0xa4, 0xa4, 0x01, 0x02) 54 IO(Decode16, 0xa8, 0xa8, 0x01, 0x02) 55 IO(Decode16, 0xac, 0xac, 0x01, 0x02) 56 IO(Decode16, 0xb0, 0xb0, 0x01, 0x02) 57 IO(Decode16, 0xb4, 0xb4, 0x01, 0x02) 58 IO(Decode16, 0xb8, 0xb8, 0x01, 0x02) 59 IO(Decode16, 0xbc, 0xbc, 0x01, 0x02) 60 IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02) 61 IRQNoFlags () { 2 } 62 }) 63 } 64 65 /* 8254 timer */ 66 Device (TIMR) 67 { 68 Name(_HID, EISAID("PNP0100")) 69 Name(_CRS, ResourceTemplate() 70 { 71 IO(Decode16, 0x40, 0x40, 0x01, 0x04) 72 IO(Decode16, 0x50, 0x50, 0x10, 0x04) 73 IRQNoFlags() { 0 } 74 }) 75 } 76 77 /* HPET */ 78 Device (HPET) 79 { 80 Name(_HID, EISAID("PNP0103")) 81 Name(_CID, 0x010CD041) 82 Name(_CRS, ResourceTemplate() 83 { 84 Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE) 85 }) 86 87 Method(_STA) 88 { 89 Return (STA_VISIBLE) 90 } 91 } 92 93 /* Internal UART */ 94 Device (IURT) 95 { 96 Name(_HID, EISAID("PNP0501")) 97 Name(_UID, 1) 98 99 Method(_STA, 0, Serialized) 100 { 101 /* 102 * TODO: 103 * 104 * Need to hide the internal UART depending on whether 105 * internal UART is enabled or not so that external 106 * SuperIO UART can be exposed to system. 107 */ 108 Store(1, UI3E) 109 Store(1, UI4E) 110 Store(1, C1EN) 111 Return (STA_VISIBLE) 112 113 } 114 115 Method(_DIS, 0, Serialized) 116 { 117 Store(0, UI3E) 118 Store(0, UI4E) 119 Store(0, C1EN) 120 } 121 122 Method(_CRS, 0, Serialized) 123 { 124 Name(BUF0, ResourceTemplate() 125 { 126 IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08) 127 IRQNoFlags() { 3 } 128 }) 129 130 Name(BUF1, ResourceTemplate() 131 { 132 IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08) 133 IRQNoFlags() { 4 } 134 }) 135 136 If (LLessEqual(SRID, 0x04)) { 137 Return (BUF0) 138 } Else { 139 Return (BUF1) 140 } 141 } 142 } 143 144 /* Real Time Clock */ 145 Device (RTC) 146 { 147 Name(_HID, EISAID("PNP0B00")) 148 Name(_CRS, ResourceTemplate() 149 { 150 IO(Decode16, 0x70, 0x70, 1, 8) 151 /* 152 * Disable as Windows doesn't like it, and systems 153 * don't seem to use it 154 */ 155 /* IRQNoFlags() { 8 } */ 156 }) 157 } 158 159 /* LPC device: Resource consumption */ 160 Device (LDRC) 161 { 162 Name(_HID, EISAID("PNP0C02")) 163 Name(_UID, 2) 164 165 Name(RBUF, ResourceTemplate() 166 { 167 IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */ 168 IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */ 169 IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */ 170 IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */ 171 IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */ 172 IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */ 173 IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */ 174 }) 175 176 Method(_CRS, 0, NotSerialized) 177 { 178 Return (RBUF) 179 } 180 } 181} 182