1 /* 2 * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ASM_ACPI_S3_H__ 8 #define __ASM_ACPI_S3_H__ 9 10 /* PM1_STATUS register */ 11 #define WAK_STS (1 << 15) 12 #define PCIEXPWAK_STS (1 << 14) 13 #define RTC_STS (1 << 10) 14 #define SLPBTN_STS (1 << 9) 15 #define PWRBTN_STS (1 << 8) 16 #define GBL_STS (1 << 5) 17 #define BM_STS (1 << 4) 18 #define TMR_STS (1 << 0) 19 20 /* PM1_CNT register */ 21 #define SLP_EN (1 << 13) 22 #define SLP_TYP_SHIFT 10 23 #define SLP_TYP (7 << SLP_TYP_SHIFT) 24 #define SLP_TYP_S0 0 25 #define SLP_TYP_S1 1 26 #define SLP_TYP_S3 5 27 #define SLP_TYP_S4 6 28 #define SLP_TYP_S5 7 29 30 enum acpi_sleep_state { 31 ACPI_S0, 32 ACPI_S1, 33 ACPI_S2, 34 ACPI_S3, 35 ACPI_S4, 36 ACPI_S5, 37 }; 38 39 /** 40 * acpi_sleep_from_pm1() - get ACPI-defined sleep state from PM1_CNT register 41 * 42 * @pm1_cnt: PM1_CNT register value 43 * @return: ACPI-defined sleep state if given valid PM1_CNT register value, 44 * -EINVAL otherwise. 45 */ 46 static inline enum acpi_sleep_state acpi_sleep_from_pm1(u32 pm1_cnt) 47 { 48 switch ((pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { 49 case SLP_TYP_S0: 50 return ACPI_S0; 51 case SLP_TYP_S1: 52 return ACPI_S1; 53 case SLP_TYP_S3: 54 return ACPI_S3; 55 case SLP_TYP_S4: 56 return ACPI_S4; 57 case SLP_TYP_S5: 58 return ACPI_S5; 59 } 60 61 return -EINVAL; 62 } 63 64 /** 65 * chipset_prev_sleep_state() - Get chipset previous sleep state 66 * 67 * This returns chipset previous sleep state from ACPI registers. 68 * Platform codes must supply this routine in order to support ACPI S3. 69 * 70 * @return ACPI_S0/S1/S2/S3/S4/S5. 71 */ 72 enum acpi_sleep_state chipset_prev_sleep_state(void); 73 74 /** 75 * chipset_clear_sleep_state() - Clear chipset sleep state 76 * 77 * This clears chipset sleep state in ACPI registers. 78 * Platform codes must supply this routine in order to support ACPI S3. 79 */ 80 void chipset_clear_sleep_state(void); 81 82 #endif /* __ASM_ACPI_S3_H__ */ 83