14372c111SBin Meng /* 24372c111SBin Meng * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> 34372c111SBin Meng * 44372c111SBin Meng * SPDX-License-Identifier: GPL-2.0+ 54372c111SBin Meng */ 64372c111SBin Meng 74372c111SBin Meng #ifndef __ASM_ACPI_S3_H__ 84372c111SBin Meng #define __ASM_ACPI_S3_H__ 94372c111SBin Meng 104372c111SBin Meng /* PM1_STATUS register */ 114372c111SBin Meng #define WAK_STS (1 << 15) 124372c111SBin Meng #define PCIEXPWAK_STS (1 << 14) 134372c111SBin Meng #define RTC_STS (1 << 10) 144372c111SBin Meng #define SLPBTN_STS (1 << 9) 154372c111SBin Meng #define PWRBTN_STS (1 << 8) 164372c111SBin Meng #define GBL_STS (1 << 5) 174372c111SBin Meng #define BM_STS (1 << 4) 184372c111SBin Meng #define TMR_STS (1 << 0) 194372c111SBin Meng 204372c111SBin Meng /* PM1_CNT register */ 214372c111SBin Meng #define SLP_EN (1 << 13) 224372c111SBin Meng #define SLP_TYP_SHIFT 10 234372c111SBin Meng #define SLP_TYP (7 << SLP_TYP_SHIFT) 244372c111SBin Meng #define SLP_TYP_S0 0 254372c111SBin Meng #define SLP_TYP_S1 1 264372c111SBin Meng #define SLP_TYP_S3 5 274372c111SBin Meng #define SLP_TYP_S4 6 284372c111SBin Meng #define SLP_TYP_S5 7 294372c111SBin Meng 304372c111SBin Meng enum acpi_sleep_state { 314372c111SBin Meng ACPI_S0, 324372c111SBin Meng ACPI_S1, 334372c111SBin Meng ACPI_S2, 344372c111SBin Meng ACPI_S3, 354372c111SBin Meng ACPI_S4, 364372c111SBin Meng ACPI_S5, 374372c111SBin Meng }; 384372c111SBin Meng 394372c111SBin Meng /** 404372c111SBin Meng * acpi_sleep_from_pm1() - get ACPI-defined sleep state from PM1_CNT register 414372c111SBin Meng * 424372c111SBin Meng * @pm1_cnt: PM1_CNT register value 434372c111SBin Meng * @return: ACPI-defined sleep state if given valid PM1_CNT register value, 444372c111SBin Meng * -EINVAL otherwise. 454372c111SBin Meng */ 464372c111SBin Meng static inline enum acpi_sleep_state acpi_sleep_from_pm1(u32 pm1_cnt) 474372c111SBin Meng { 484372c111SBin Meng switch ((pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { 494372c111SBin Meng case SLP_TYP_S0: 504372c111SBin Meng return ACPI_S0; 514372c111SBin Meng case SLP_TYP_S1: 524372c111SBin Meng return ACPI_S1; 534372c111SBin Meng case SLP_TYP_S3: 544372c111SBin Meng return ACPI_S3; 554372c111SBin Meng case SLP_TYP_S4: 564372c111SBin Meng return ACPI_S4; 574372c111SBin Meng case SLP_TYP_S5: 584372c111SBin Meng return ACPI_S5; 594372c111SBin Meng } 604372c111SBin Meng 614372c111SBin Meng return -EINVAL; 624372c111SBin Meng } 634372c111SBin Meng 64*1206723bSBin Meng /** 65*1206723bSBin Meng * chipset_prev_sleep_state() - Get chipset previous sleep state 66*1206723bSBin Meng * 67*1206723bSBin Meng * This returns chipset previous sleep state from ACPI registers. 68*1206723bSBin Meng * Platform codes must supply this routine in order to support ACPI S3. 69*1206723bSBin Meng * 70*1206723bSBin Meng * @return ACPI_S0/S1/S2/S3/S4/S5. 71*1206723bSBin Meng */ 72*1206723bSBin Meng enum acpi_sleep_state chipset_prev_sleep_state(void); 73*1206723bSBin Meng 74*1206723bSBin Meng /** 75*1206723bSBin Meng * chipset_clear_sleep_state() - Clear chipset sleep state 76*1206723bSBin Meng * 77*1206723bSBin Meng * This clears chipset sleep state in ACPI registers. 78*1206723bSBin Meng * Platform codes must supply this routine in order to support ACPI S3. 79*1206723bSBin Meng */ 80*1206723bSBin Meng void chipset_clear_sleep_state(void); 81*1206723bSBin Meng 824372c111SBin Meng #endif /* __ASM_ACPI_S3_H__ */ 83