1/* 2 * Copyright (C) 2016 Google, Inc 3 * Written by Simon Glass <sjg@chromium.org> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#include <config.h> 9 10#ifdef CONFIG_ROM_SIZE 11/ { 12 binman { 13 filename = "u-boot.rom"; 14 end-at-4gb; 15 sort-by-pos; 16 pad-byte = <0xff>; 17 size = <CONFIG_ROM_SIZE>; 18#ifdef CONFIG_HAVE_INTEL_ME 19 intel-descriptor { 20 filename = CONFIG_FLASH_DESCRIPTOR_FILE; 21 }; 22 intel-me { 23 filename = CONFIG_INTEL_ME_FILE; 24 }; 25#endif 26#ifdef CONFIG_SPL 27 u-boot-spl-with-ucode-ptr { 28 pos = <CONFIG_SPL_TEXT_BASE>; 29 }; 30 31 u-boot-dtb-with-ucode2 { 32 type = "u-boot-dtb-with-ucode"; 33 }; 34 u-boot { 35 pos = <0xfff00000>; 36 }; 37#else 38 u-boot-with-ucode-ptr { 39 pos = <CONFIG_SYS_TEXT_BASE>; 40 }; 41#endif 42 u-boot-dtb-with-ucode { 43 }; 44 u-boot-ucode { 45 align = <16>; 46 }; 47#ifdef CONFIG_HAVE_MRC 48 intel-mrc { 49 pos = <CONFIG_X86_MRC_ADDR>; 50 }; 51#endif 52#ifdef CONFIG_HAVE_FSP 53 intel-fsp { 54 filename = CONFIG_FSP_FILE; 55 pos = <CONFIG_FSP_ADDR>; 56 }; 57#endif 58#ifdef CONFIG_HAVE_CMC 59 intel-cmc { 60 filename = CONFIG_CMC_FILE; 61 pos = <CONFIG_CMC_ADDR>; 62 }; 63#endif 64#ifdef CONFIG_HAVE_VGA_BIOS 65 intel-vga { 66 filename = CONFIG_VGA_BIOS_FILE; 67 pos = <CONFIG_VGA_BIOS_ADDR>; 68 }; 69#endif 70#ifdef CONFIG_HAVE_REFCODE 71 intel-refcode { 72 pos = <CONFIG_X86_REFCODE_ADDR>; 73 }; 74#endif 75#ifdef CONFIG_SPL 76 x86-start16-spl { 77 pos = <CONFIG_SYS_X86_START16>; 78 }; 79#else 80 x86-start16 { 81 pos = <CONFIG_SYS_X86_START16>; 82 }; 83#endif 84 }; 85}; 86#endif 87