1/* 2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/interrupt-router/intel-irq.h> 10 11/* ICH9 IRQ router has discrete PIRQ control registers */ 12#undef PIRQE 13#undef PIRQF 14#undef PIRQG 15#undef PIRQH 16#define PIRQE 8 17#define PIRQF 9 18#define PIRQG 10 19#define PIRQH 11 20 21/include/ "skeleton.dtsi" 22/include/ "serial.dtsi" 23/include/ "keyboard.dtsi" 24/include/ "rtc.dtsi" 25/include/ "tsc_timer.dtsi" 26 27/ { 28 model = "QEMU x86 (Q35)"; 29 compatible = "qemu,x86"; 30 31 config { 32 silent_console = <0>; 33 u-boot,no-apm-finalize; 34 }; 35 36 chosen { 37 stdout-path = "/serial"; 38 }; 39 40 cpus { 41 #address-cells = <1>; 42 #size-cells = <0>; 43 u-boot,dm-pre-reloc; 44 45 cpu@0 { 46 device_type = "cpu"; 47 compatible = "cpu-qemu"; 48 u-boot,dm-pre-reloc; 49 reg = <0>; 50 intel,apic-id = <0>; 51 }; 52 }; 53 54 tsc-timer { 55 clock-frequency = <1000000000>; 56 }; 57 58 pci { 59 compatible = "pci-x86"; 60 #address-cells = <3>; 61 #size-cells = <2>; 62 u-boot,dm-pre-reloc; 63 ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000 64 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 65 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 66 67 pch@1f,0 { 68 reg = <0x0000f800 0 0 0 0>; 69 compatible = "intel,pch9"; 70 u-boot,dm-pre-reloc; 71 72 irq-router { 73 compatible = "intel,irq-router"; 74 u-boot,dm-pre-reloc; 75 intel,pirq-config = "pci"; 76 intel,actl-8bit; 77 intel,actl-addr = <0x44>; 78 intel,pirq-link = <0x60 8>; 79 intel,pirq-mask = <0x0e40>; 80 intel,pirq-routing = < 81 /* e1000 NIC */ 82 PCI_BDF(0, 2, 0) INTA PIRQG 83 /* ICH9 UHCI */ 84 PCI_BDF(0, 29, 0) INTA PIRQA 85 PCI_BDF(0, 29, 1) INTB PIRQB 86 PCI_BDF(0, 29, 2) INTC PIRQC 87 /* ICH9 EHCI */ 88 PCI_BDF(0, 29, 7) INTD PIRQD 89 /* ICH9 SATA */ 90 PCI_BDF(0, 31, 2) INTA PIRQA 91 >; 92 }; 93 }; 94 }; 95 96}; 97