1/* 2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/dts-v1/; 8 9#include <asm/arch-baytrail/fsp/fsp_configs.h> 10#include <dt-bindings/gpio/x86-gpio.h> 11#include <dt-bindings/interrupt-router/intel-irq.h> 12 13/include/ "skeleton.dtsi" 14/include/ "serial.dtsi" 15/include/ "rtc.dtsi" 16/include/ "tsc_timer.dtsi" 17/include/ "coreboot_fb.dtsi" 18 19/ { 20 model = "Intel Minnowboard Max"; 21 compatible = "intel,minnowmax", "intel,baytrail"; 22 23 aliases { 24 serial0 = &serial; 25 spi0 = &spi; 26 }; 27 28 config { 29 silent_console = <0>; 30 }; 31 32 pch_pinctrl { 33 compatible = "intel,x86-pinctrl"; 34 reg = <0 0>; 35 36 /* GPIO E0 */ 37 soc_gpio_s5_0@0 { 38 gpio-offset = <0x80 0>; 39 mode-gpio; 40 output-value = <0>; 41 direction = <PIN_OUTPUT>; 42 }; 43 44 /* GPIO E1 */ 45 soc_gpio_s5_1@0 { 46 gpio-offset = <0x80 1>; 47 mode-gpio; 48 output-value = <0>; 49 direction = <PIN_OUTPUT>; 50 }; 51 52 /* GPIO E2 */ 53 soc_gpio_s5_2@0 { 54 gpio-offset = <0x80 2>; 55 mode-gpio; 56 output-value = <0>; 57 direction = <PIN_OUTPUT>; 58 }; 59 60 pin_usb_host_en0@0 { 61 gpio-offset = <0x80 8>; 62 mode-gpio; 63 output-value = <1>; 64 direction = <PIN_OUTPUT>; 65 }; 66 67 pin_usb_host_en1@0 { 68 gpio-offset = <0x80 9>; 69 mode-gpio; 70 output-value = <1>; 71 direction = <PIN_OUTPUT>; 72 }; 73 74 /* 75 * As of today, the latest version FSP (gold4) for BayTrail 76 * misses the PAD configuration of the SD controller's Card 77 * Detect signal. The default PAD value for the CD pin sets 78 * the pin to work in GPIO mode, which causes card detect 79 * status cannot be reflected by the Present State register 80 * in the SD controller (bit 16 & bit 18 are always zero). 81 * 82 * Configure this pin to function 1 (SD controller). 83 */ 84 sdmmc3_cd@0 { 85 pad-offset = <0x3a0>; 86 mode-func = <1>; 87 }; 88 }; 89 90 chosen { 91 stdout-path = "/serial"; 92 }; 93 94 cpus { 95 #address-cells = <1>; 96 #size-cells = <0>; 97 98 cpu@0 { 99 device_type = "cpu"; 100 compatible = "intel,baytrail-cpu"; 101 reg = <0>; 102 intel,apic-id = <0>; 103 }; 104 105 cpu@1 { 106 device_type = "cpu"; 107 compatible = "intel,baytrail-cpu"; 108 reg = <1>; 109 intel,apic-id = <4>; 110 }; 111 112 }; 113 114 pci { 115 compatible = "intel,pci-baytrail", "pci-x86"; 116 #address-cells = <3>; 117 #size-cells = <2>; 118 u-boot,dm-pre-reloc; 119 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 120 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 121 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 122 123 pch@1f,0 { 124 reg = <0x0000f800 0 0 0 0>; 125 compatible = "pci8086,0f1c", "intel,pch9"; 126 #address-cells = <1>; 127 #size-cells = <1>; 128 129 irq-router { 130 compatible = "intel,irq-router"; 131 intel,pirq-config = "ibase"; 132 intel,ibase-offset = <0x50>; 133 intel,actl-addr = <0>; 134 intel,pirq-link = <8 8>; 135 intel,pirq-mask = <0xdee0>; 136 intel,pirq-routing = < 137 /* BayTrail PCI devices */ 138 PCI_BDF(0, 2, 0) INTA PIRQA 139 PCI_BDF(0, 3, 0) INTA PIRQA 140 PCI_BDF(0, 16, 0) INTA PIRQA 141 PCI_BDF(0, 17, 0) INTA PIRQA 142 PCI_BDF(0, 18, 0) INTA PIRQA 143 PCI_BDF(0, 19, 0) INTA PIRQA 144 PCI_BDF(0, 20, 0) INTA PIRQA 145 PCI_BDF(0, 21, 0) INTA PIRQA 146 PCI_BDF(0, 22, 0) INTA PIRQA 147 PCI_BDF(0, 23, 0) INTA PIRQA 148 PCI_BDF(0, 24, 0) INTA PIRQA 149 PCI_BDF(0, 24, 1) INTC PIRQC 150 PCI_BDF(0, 24, 2) INTD PIRQD 151 PCI_BDF(0, 24, 3) INTB PIRQB 152 PCI_BDF(0, 24, 4) INTA PIRQA 153 PCI_BDF(0, 24, 5) INTC PIRQC 154 PCI_BDF(0, 24, 6) INTD PIRQD 155 PCI_BDF(0, 24, 7) INTB PIRQB 156 PCI_BDF(0, 26, 0) INTA PIRQA 157 PCI_BDF(0, 27, 0) INTA PIRQA 158 PCI_BDF(0, 28, 0) INTA PIRQA 159 PCI_BDF(0, 28, 1) INTB PIRQB 160 PCI_BDF(0, 28, 2) INTC PIRQC 161 PCI_BDF(0, 28, 3) INTD PIRQD 162 PCI_BDF(0, 29, 0) INTA PIRQA 163 PCI_BDF(0, 30, 0) INTA PIRQA 164 PCI_BDF(0, 30, 1) INTD PIRQD 165 PCI_BDF(0, 30, 2) INTB PIRQB 166 PCI_BDF(0, 30, 3) INTC PIRQC 167 PCI_BDF(0, 30, 4) INTD PIRQD 168 PCI_BDF(0, 30, 5) INTB PIRQB 169 PCI_BDF(0, 31, 3) INTB PIRQB 170 171 /* 172 * PCIe root ports downstream 173 * interrupts 174 */ 175 PCI_BDF(1, 0, 0) INTA PIRQA 176 PCI_BDF(1, 0, 0) INTB PIRQB 177 PCI_BDF(1, 0, 0) INTC PIRQC 178 PCI_BDF(1, 0, 0) INTD PIRQD 179 PCI_BDF(2, 0, 0) INTA PIRQB 180 PCI_BDF(2, 0, 0) INTB PIRQC 181 PCI_BDF(2, 0, 0) INTC PIRQD 182 PCI_BDF(2, 0, 0) INTD PIRQA 183 PCI_BDF(3, 0, 0) INTA PIRQC 184 PCI_BDF(3, 0, 0) INTB PIRQD 185 PCI_BDF(3, 0, 0) INTC PIRQA 186 PCI_BDF(3, 0, 0) INTD PIRQB 187 PCI_BDF(4, 0, 0) INTA PIRQD 188 PCI_BDF(4, 0, 0) INTB PIRQA 189 PCI_BDF(4, 0, 0) INTC PIRQB 190 PCI_BDF(4, 0, 0) INTD PIRQC 191 >; 192 }; 193 194 spi: spi { 195 #address-cells = <1>; 196 #size-cells = <0>; 197 compatible = "intel,ich9-spi"; 198 spi-flash@0 { 199 #address-cells = <1>; 200 #size-cells = <1>; 201 reg = <0>; 202 compatible = "stmicro,n25q064a", 203 "spi-flash"; 204 memory-map = <0xff800000 0x00800000>; 205 rw-mrc-cache { 206 label = "rw-mrc-cache"; 207 reg = <0x006f0000 0x00010000>; 208 }; 209 }; 210 }; 211 212 gpioa { 213 compatible = "intel,ich6-gpio"; 214 u-boot,dm-pre-reloc; 215 reg = <0 0x20>; 216 bank-name = "A"; 217 use-lvl-write-cache; 218 }; 219 220 gpiob { 221 compatible = "intel,ich6-gpio"; 222 u-boot,dm-pre-reloc; 223 reg = <0x20 0x20>; 224 bank-name = "B"; 225 use-lvl-write-cache; 226 }; 227 228 gpioc { 229 compatible = "intel,ich6-gpio"; 230 u-boot,dm-pre-reloc; 231 reg = <0x40 0x20>; 232 bank-name = "C"; 233 use-lvl-write-cache; 234 }; 235 236 gpiod { 237 compatible = "intel,ich6-gpio"; 238 u-boot,dm-pre-reloc; 239 reg = <0x60 0x20>; 240 bank-name = "D"; 241 use-lvl-write-cache; 242 }; 243 244 gpioe { 245 compatible = "intel,ich6-gpio"; 246 u-boot,dm-pre-reloc; 247 reg = <0x80 0x20>; 248 bank-name = "E"; 249 use-lvl-write-cache; 250 }; 251 252 gpiof { 253 compatible = "intel,ich6-gpio"; 254 u-boot,dm-pre-reloc; 255 reg = <0xA0 0x20>; 256 bank-name = "F"; 257 use-lvl-write-cache; 258 }; 259 }; 260 }; 261 262 fsp { 263 compatible = "intel,baytrail-fsp"; 264 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>; 265 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>; 266 fsp,mrc-init-spd-addr1 = <0xa0>; 267 fsp,mrc-init-spd-addr2 = <0xa2>; 268 fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>; 269 fsp,enable-sdio; 270 fsp,enable-sdcard; 271 fsp,enable-hsuart1; 272 fsp,enable-spi; 273 fsp,enable-sata; 274 fsp,sata-mode = <SATA_MODE_AHCI>; 275 fsp,lpe-mode = <LPE_MODE_PCI>; 276 fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>; 277 fsp,enable-dma0; 278 fsp,enable-dma1; 279 fsp,enable-i2c0; 280 fsp,enable-i2c1; 281 fsp,enable-i2c2; 282 fsp,enable-i2c3; 283 fsp,enable-i2c4; 284 fsp,enable-i2c5; 285 fsp,enable-i2c6; 286 fsp,enable-pwm0; 287 fsp,enable-pwm1; 288 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>; 289 fsp,aperture-size = <APERTURE_SIZE_256MB>; 290 fsp,gtt-size = <GTT_SIZE_2MB>; 291 fsp,scc-mode = <SCC_MODE_PCI>; 292 fsp,os-selection = <OS_SELECTION_LINUX>; 293 fsp,emmc45-ddr50-enabled; 294 fsp,emmc45-retune-timer-value = <8>; 295 fsp,enable-igd; 296 fsp,enable-memory-down; 297 fsp,memory-down-params { 298 compatible = "intel,baytrail-fsp-mdp"; 299 fsp,dram-speed = <DRAM_SPEED_1066MTS>; 300 fsp,dram-type = <DRAM_TYPE_DDR3L>; 301 fsp,dimm-0-enable; 302 fsp,dimm-width = <DIMM_WIDTH_X16>; 303 fsp,dimm-density = <DIMM_DENSITY_4GBIT>; 304 fsp,dimm-bus-width = <DIMM_BUS_WIDTH_64BITS>; 305 fsp,dimm-sides = <DIMM_SIDES_1RANKS>; 306 fsp,dimm-tcl = <0xb>; 307 fsp,dimm-trpt-rcd = <0xb>; 308 fsp,dimm-twr = <0xc>; 309 fsp,dimm-twtr = <6>; 310 fsp,dimm-trrd = <6>; 311 fsp,dimm-trtp = <6>; 312 fsp,dimm-tfaw = <0x14>; 313 }; 314 }; 315 316 microcode { 317 update@0 { 318#include "microcode/m0130673325.dtsi" 319 }; 320 update@1 { 321#include "microcode/m0130679907.dtsi" 322 }; 323 }; 324 325}; 326