1/* 2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/gpio/x86-gpio.h> 10#include <dt-bindings/interrupt-router/intel-irq.h> 11 12/include/ "skeleton.dtsi" 13/include/ "serial.dtsi" 14/include/ "rtc.dtsi" 15/include/ "tsc_timer.dtsi" 16 17/ { 18 model = "Intel Minnowboard Max"; 19 compatible = "intel,minnowmax", "intel,baytrail"; 20 21 aliases { 22 serial0 = &serial; 23 spi0 = &spi; 24 }; 25 26 config { 27 silent_console = <0>; 28 }; 29 30 pch_pinctrl { 31 compatible = "intel,x86-pinctrl"; 32 reg = <0 0>; 33 34 /* GPIO E0 */ 35 soc_gpio_s5_0@0 { 36 gpio-offset = <0x80 0>; 37 pad-offset = <0x1d0>; 38 mode-gpio; 39 output-value = <0>; 40 direction = <PIN_OUTPUT>; 41 }; 42 43 /* GPIO E1 */ 44 soc_gpio_s5_1@0 { 45 gpio-offset = <0x80 1>; 46 pad-offset = <0x210>; 47 mode-gpio; 48 output-value = <0>; 49 direction = <PIN_OUTPUT>; 50 }; 51 52 /* GPIO E2 */ 53 soc_gpio_s5_2@0 { 54 gpio-offset = <0x80 2>; 55 pad-offset = <0x1e0>; 56 mode-gpio; 57 output-value = <0>; 58 direction = <PIN_OUTPUT>; 59 }; 60 61 pin_usb_host_en0@0 { 62 gpio-offset = <0x80 8>; 63 pad-offset = <0x260>; 64 mode-gpio; 65 output-value = <1>; 66 direction = <PIN_OUTPUT>; 67 }; 68 69 pin_usb_host_en1@0 { 70 gpio-offset = <0x80 9>; 71 pad-offset = <0x250>; 72 mode-gpio; 73 output-value = <1>; 74 direction = <PIN_OUTPUT>; 75 }; 76 77 /* 78 * As of today, the latest version FSP (gold4) for BayTrail 79 * misses the PAD configuration of the SD controller's Card 80 * Detect signal. The default PAD value for the CD pin sets 81 * the pin to work in GPIO mode, which causes card detect 82 * status cannot be reflected by the Present State register 83 * in the SD controller (bit 16 & bit 18 are always zero). 84 * 85 * Configure this pin to function 1 (SD controller). 86 */ 87 sdmmc3_cd@0 { 88 pad-offset = <0x3a0>; 89 mode-func = <1>; 90 }; 91 }; 92 93 chosen { 94 stdout-path = "/serial"; 95 }; 96 97 cpus { 98 #address-cells = <1>; 99 #size-cells = <0>; 100 101 cpu@0 { 102 device_type = "cpu"; 103 compatible = "intel,baytrail-cpu"; 104 reg = <0>; 105 intel,apic-id = <0>; 106 }; 107 108 cpu@1 { 109 device_type = "cpu"; 110 compatible = "intel,baytrail-cpu"; 111 reg = <1>; 112 intel,apic-id = <4>; 113 }; 114 115 }; 116 117 pci { 118 compatible = "intel,pci-baytrail", "pci-x86"; 119 #address-cells = <3>; 120 #size-cells = <2>; 121 u-boot,dm-pre-reloc; 122 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 123 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 124 0x01000000 0x0 0x2000 0x2000 0 0xe000>; 125 126 pch@1f,0 { 127 reg = <0x0000f800 0 0 0 0>; 128 compatible = "pci8086,0f1c", "intel,pch9"; 129 #address-cells = <1>; 130 #size-cells = <1>; 131 132 irq-router { 133 compatible = "intel,irq-router"; 134 intel,pirq-config = "ibase"; 135 intel,ibase-offset = <0x50>; 136 intel,actl-addr = <0>; 137 intel,pirq-link = <8 8>; 138 intel,pirq-mask = <0xdee0>; 139 intel,pirq-routing = < 140 /* BayTrail PCI devices */ 141 PCI_BDF(0, 2, 0) INTA PIRQA 142 PCI_BDF(0, 3, 0) INTA PIRQA 143 PCI_BDF(0, 16, 0) INTA PIRQA 144 PCI_BDF(0, 17, 0) INTA PIRQA 145 PCI_BDF(0, 18, 0) INTA PIRQA 146 PCI_BDF(0, 19, 0) INTA PIRQA 147 PCI_BDF(0, 20, 0) INTA PIRQA 148 PCI_BDF(0, 21, 0) INTA PIRQA 149 PCI_BDF(0, 22, 0) INTA PIRQA 150 PCI_BDF(0, 23, 0) INTA PIRQA 151 PCI_BDF(0, 24, 0) INTA PIRQA 152 PCI_BDF(0, 24, 1) INTC PIRQC 153 PCI_BDF(0, 24, 2) INTD PIRQD 154 PCI_BDF(0, 24, 3) INTB PIRQB 155 PCI_BDF(0, 24, 4) INTA PIRQA 156 PCI_BDF(0, 24, 5) INTC PIRQC 157 PCI_BDF(0, 24, 6) INTD PIRQD 158 PCI_BDF(0, 24, 7) INTB PIRQB 159 PCI_BDF(0, 26, 0) INTA PIRQA 160 PCI_BDF(0, 27, 0) INTA PIRQA 161 PCI_BDF(0, 28, 0) INTA PIRQA 162 PCI_BDF(0, 28, 1) INTB PIRQB 163 PCI_BDF(0, 28, 2) INTC PIRQC 164 PCI_BDF(0, 28, 3) INTD PIRQD 165 PCI_BDF(0, 29, 0) INTA PIRQA 166 PCI_BDF(0, 30, 0) INTA PIRQA 167 PCI_BDF(0, 30, 1) INTD PIRQD 168 PCI_BDF(0, 30, 2) INTB PIRQB 169 PCI_BDF(0, 30, 3) INTC PIRQC 170 PCI_BDF(0, 30, 4) INTD PIRQD 171 PCI_BDF(0, 30, 5) INTB PIRQB 172 PCI_BDF(0, 31, 3) INTB PIRQB 173 174 /* 175 * PCIe root ports downstream 176 * interrupts 177 */ 178 PCI_BDF(1, 0, 0) INTA PIRQA 179 PCI_BDF(1, 0, 0) INTB PIRQB 180 PCI_BDF(1, 0, 0) INTC PIRQC 181 PCI_BDF(1, 0, 0) INTD PIRQD 182 PCI_BDF(2, 0, 0) INTA PIRQB 183 PCI_BDF(2, 0, 0) INTB PIRQC 184 PCI_BDF(2, 0, 0) INTC PIRQD 185 PCI_BDF(2, 0, 0) INTD PIRQA 186 PCI_BDF(3, 0, 0) INTA PIRQC 187 PCI_BDF(3, 0, 0) INTB PIRQD 188 PCI_BDF(3, 0, 0) INTC PIRQA 189 PCI_BDF(3, 0, 0) INTD PIRQB 190 PCI_BDF(4, 0, 0) INTA PIRQD 191 PCI_BDF(4, 0, 0) INTB PIRQA 192 PCI_BDF(4, 0, 0) INTC PIRQB 193 PCI_BDF(4, 0, 0) INTD PIRQC 194 >; 195 }; 196 197 spi: spi { 198 #address-cells = <1>; 199 #size-cells = <0>; 200 compatible = "intel,ich9-spi"; 201 spi-flash@0 { 202 #address-cells = <1>; 203 #size-cells = <1>; 204 reg = <0>; 205 compatible = "stmicro,n25q064a", 206 "spi-flash"; 207 memory-map = <0xff800000 0x00800000>; 208 rw-mrc-cache { 209 label = "rw-mrc-cache"; 210 reg = <0x006f0000 0x00010000>; 211 }; 212 }; 213 }; 214 215 gpioa { 216 compatible = "intel,ich6-gpio"; 217 u-boot,dm-pre-reloc; 218 reg = <0 0x20>; 219 bank-name = "A"; 220 }; 221 222 gpiob { 223 compatible = "intel,ich6-gpio"; 224 u-boot,dm-pre-reloc; 225 reg = <0x20 0x20>; 226 bank-name = "B"; 227 }; 228 229 gpioc { 230 compatible = "intel,ich6-gpio"; 231 u-boot,dm-pre-reloc; 232 reg = <0x40 0x20>; 233 bank-name = "C"; 234 }; 235 236 gpiod { 237 compatible = "intel,ich6-gpio"; 238 u-boot,dm-pre-reloc; 239 reg = <0x60 0x20>; 240 bank-name = "D"; 241 }; 242 243 gpioe { 244 compatible = "intel,ich6-gpio"; 245 u-boot,dm-pre-reloc; 246 reg = <0x80 0x20>; 247 bank-name = "E"; 248 }; 249 250 gpiof { 251 compatible = "intel,ich6-gpio"; 252 u-boot,dm-pre-reloc; 253 reg = <0xA0 0x20>; 254 bank-name = "F"; 255 }; 256 }; 257 }; 258 259 fsp { 260 compatible = "intel,baytrail-fsp"; 261 fsp,mrc-init-tseg-size = <0>; 262 fsp,mrc-init-mmio-size = <0x800>; 263 fsp,mrc-init-spd-addr1 = <0xa0>; 264 fsp,mrc-init-spd-addr2 = <0xa2>; 265 fsp,emmc-boot-mode = <1>; 266 fsp,enable-sdio; 267 fsp,enable-sdcard; 268 fsp,enable-hsuart1; 269 fsp,enable-spi; 270 fsp,enable-sata; 271 fsp,sata-mode = <1>; 272 fsp,enable-lpe; 273 fsp,lpss-sio-enable-pci-mode; 274 fsp,enable-dma0; 275 fsp,enable-dma1; 276 fsp,enable-i2c0; 277 fsp,enable-i2c1; 278 fsp,enable-i2c2; 279 fsp,enable-i2c3; 280 fsp,enable-i2c4; 281 fsp,enable-i2c5; 282 fsp,enable-i2c6; 283 fsp,enable-pwm0; 284 fsp,enable-pwm1; 285 fsp,igd-dvmt50-pre-alloc = <2>; 286 fsp,aperture-size = <2>; 287 fsp,gtt-size = <2>; 288 fsp,serial-debug-port-address = <0x3f8>; 289 fsp,serial-debug-port-type = <1>; 290 fsp,scc-enable-pci-mode; 291 fsp,os-selection = <4>; 292 fsp,emmc45-ddr50-enabled; 293 fsp,emmc45-retune-timer-value = <8>; 294 fsp,enable-igd; 295 fsp,enable-memory-down; 296 fsp,memory-down-params { 297 compatible = "intel,baytrail-fsp-mdp"; 298 fsp,dram-speed = <1>; 299 fsp,dram-type = <1>; 300 fsp,dimm-0-enable; 301 fsp,dimm-width = <1>; 302 fsp,dimm-density = <2>; 303 fsp,dimm-bus-width = <3>; 304 fsp,dimm-sides = <0>; 305 fsp,dimm-tcl = <0xb>; 306 fsp,dimm-trpt-rcd = <0xb>; 307 fsp,dimm-twr = <0xc>; 308 fsp,dimm-twtr = <6>; 309 fsp,dimm-trrd = <6>; 310 fsp,dimm-trtp = <6>; 311 fsp,dimm-tfaw = <0x14>; 312 }; 313 }; 314 315 microcode { 316 update@0 { 317#include "microcode/m0130673325.dtsi" 318 }; 319 update@1 { 320#include "microcode/m0130679907.dtsi" 321 }; 322 }; 323 324}; 325